(MBD_DM6437_FPGA_en)DaVinci_lab5_speedway_f08_10_1_3_3(9)

Figure 8 -- Exporting Memory-Mapping for Shared memory

7. Follow the steps in Figure 9 to create a subsystem named ‘VLYNQ’, and add the

‘Multiple Subsystem Generator’ block from the Simulink Library Browser Æ Xilinx Blockset Æ Tools.

Figure 9 – Creating the VLYNQ Subsystem

Figure 10 – Adding a Multiple Subsystem Generator

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