(MBD_DM6437_FPGA_en)DaVinci_lab5_speedway_f08_10_1_3_3(8)

Figure 6 -- Adding 'DaVinci Processor' and 'dipsw' blocks

Double-click to open the ‘Davinci Processor’ GUI. Enumerate all shared memory in the model. Close the GUI when finished.

Figure 7 -- Enumerating Shared Memory

Shared memories in the System Generator model destined for the FPGA co-processor are associated with the DM6437 processor through the ‘DaVinci Processor’ VLYNQ

Interface block’s GUI. Expand all shared memories as shown above in Figure 7, and copy the information into the table below. DSP Æ FPGA indicates DM6437 writes to FPGA.

Name

Address (Hex) / (Dec) NOTE: ignore MS Hex digit

sad_roi sad_template

depth

direction

DSP Æ FPGA DSP Æ FPGA

n/a FPGA Æ DSP

min_SAD_Idx

SAD_NVals

FPGA Æ DSP

dip n/a FPGA Æ DSP

Table 1

In the following steps, the complete FPGA co-processor consisting of SAD + VLYNQ interface will be generated and memory-mapping information of table 1 exported to:

Xilinx ISE, passing memory-mapping the the VLYNQ LogiCore IP

Texas Instruments Code Composer Studio via The MathWorks Embedded Target TC6 tools

Exporting memory-mapping for shared memory is illustrated below, as presented in lecture 5.

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