(MBD_DM6437_FPGA_en)DaVinci_lab5_speedway_f08_10_1_3_3(4)

Introduction

In lab 4 we added robust flow control to the basic System Generator-based SAD model of lab 3. We then prepared the model for hardware co-simulation in anticipation of burst mode data flow between Simulink and FPGA. We ran hardware co-simulation to prove the model under test in FPGA hardware at full system clock rate as part of a larger Simulink system.

Using MPLAY, we demonstrated a method of single-stepping the system through individual frames of video to observe data at any node in the system. Armed with the confidence that the FPGA design-under-test performs as expected, we can move towards a stand-alone video system combining DSP and FPGA co-processor on the Avnet Spartan-3A DSP DaVinci board.

Experiment 1: Building the stand-alone FPGA co-processor

The starting point for the stand-alone FPGA co-processor is the final model of lab 4, which we will now augment with VLYNQ connectivity to the DM6437 DSP, as shown below.

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