(MBD_DM6437_FPGA_en)DaVinci_lab5_speedway_f08_10_1_3_3(12)

Experiment 2: Integrating the co-processor into the board-level FPGA infrastructure for the Avnet Spartan-3A DSP DaVinci Development Kit

In experiment 1 we developed the application-specific co-processor in Xilinx System Generator for DSP with MathWorks model-based design tools. In experiment 2, we will import the co-processor design into a larger system that contains the entire FPGA

infrastructure for the Avnet Spartan-3A DSP DaVinci. The design environment of choice for this task is Xilinx ISE Project Navigator.1

Lab Procedure:

1. From the Windows Start / All Programs menu, launch Xilinx Project Navigator:

Xilinx ISE Design Suite 10 Æ ISE Æ Project Navigator

2. From File Æ Open project, navigate to

3. Double click to open project davinci_coprocessor_sad_demo.ise

C:\SpeedWay\Fall_08\co_processing\lab5\avnet_s3adsp_dm6437_FPGA_top_level

Xilinx ISE Project Navigator is the main IDE for FPGA development. Although there is insufficient time to explore ISE in this seminar, Avnet and Xilinx offer a variety of introductory-level workshops featuring ISE.

1

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