(MBD_DM6437_FPGA_en)DaVinci_lab5_speedway_f08_10_1_3_3(15)

5. Highlight the top-level module ‘davinci_coprocessor_sad_demo’ and launch

‘Configure Target Device’, as shown below. This will execute all intermediate

processes in order to generate the bitstream for download to the FPGA. At this time, ensure the JTAG download cable to the board is still connected.

Figure 17 -- Generating the Bitstream for FPGA-side Stand-Alone Video System

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