(MBD_DM6437_FPGA_en)DaVinci_lab5_speedway_f08_10_1_3_3(6)

4. Next we add the Xilinx System Generator block, as shown below. System Generator

will propagate the FPGA clock period setting of 16 ns as a timing constraint for the VLYNQ interface to ISE Project Navigator. This corresponds to an FPGA system clock of 125 MHz divided by 2 on the Avnet Spartan-3A DSP DaVinci board.

The SAD engine is operated at 125 MHz (8 ns period constraint), set in the System Generator block of subsystem ‘sad’. If faster SAD computation time is desired of the

FPGA co-processor, then this clock period setting can be reduced. This is a design decision that is normally taken at step 32 in experiment 3.

Figure 4 -- Adding Xilinx System Generator block

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