基于FPGA的数字系统设计实验3控制液晶显示屏显示字符OK(8)

num_count <= 20'd4; lcd_d <= 4'h1; end

state32:begin state <= state33;

num_count <= 20'd12; lcd_e <= 1'b1; end state33:begin

state <= state34;

num_count <= 20'd2000; lcd_e <= 1'b0; end state34:begin

state <= state35;

num_count <= 20'd82000; end

//set DD RAM address state35:begin

state <= state36; num_count <= 20'd4; lcd_rs <= 1'b0; lcd_e <= 1'b0; lcd_d <= 4'h8; end

state36:begin

state <= state37;

num_count <= 20'd12; lcd_e <= 1'b1; end

state37:begin state <= state38;

num_count <= 20'd80; lcd_e <= 1'b0; end

state38:begin state <= state39;

num_count <= 20'd4; lcd_d <= 4'h0; end

state39:begin state <= state40;

num_count <= 20'd12; lcd_e <= 1'b1; end

state40:begin state <= state41;

num_count <= 20'd4000; lcd_e <= 1'b0; end

// now starts writing data to DD RAM state41:begin state <= state42; num_count <= 20'd4; lcd_rs <= 1'b1; lcd_d <= 4'h4; end

state42:begin

state <= state43;

num_count <= 20'd12; lcd_e <= 1'b1; end

state43:begin

state <= state44;

num_count <= 20'd80; lcd_e <= 1'b0; end

state44:begin

state <= state45; num_count <= 20'd4; lcd_d <= 4'hf; end state45:begin

state <= state46;

num_count <= 20'd12; lcd_e <= 1'b1; end state46:begin state <= state47;

num_count <= 20'd2000;

lcd_e <= 1'b0; end

state47:begin

state <= state48; num_count <= 20'd4; lcd_rs <= 1'b1; lcd_d <= 4'h4; end

state48:begin

state <= state49;

num_count <= 20'd12; lcd_e <= 1'b1; end

state49:begin

state <= state50;

num_count <= 20'd80; lcd_e <= 1'b0; end

state50:begin

state <= state51; num_count <= 20'd4; lcd_d <= 4'hb; end

state51:begin

state <= state52;

num_count <= 20'd12; lcd_e <= 1'b1; end

state52:begin state <= state53;

num_count <= 20'd2000; lcd_e <= 1'b0; end

state53:begin

state <= state54; num_count <= 20'd4; lcd_rs <= 1'b1; lcd_d <= 4'h2;

end

state54:begin state <= state55;

num_count <= 20'd12; lcd_e <= 1'b1; end state55:begin

state <= state56;

num_count <= 20'd80; lcd_e <= 1'b0; end

state56:begin

state <= state57; num_count <= 20'd4; lcd_d <= 4'h1; end state57:begin

state <= state58;

num_count <= 20'd12; lcd_e <= 1'b1; end state58:begin

state <= state59;

num_count <= 20'd4000; lcd_e <= 1'b0; end

state59:begin

state <= state35;

num_count <= 20'd800; end default:begin

state <= state1; num_count <= 20'd800; end endcase endmodule

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