基于FPGA的数字系统设计实验3控制液晶显示屏显示字符OK(6)

num_count <= 20'd4; lcd_d <= 4'hf; end state45:begin

state <= state46;

num_count <= 20'd12; lcd_e <= 1'b1;

end state46:begin

state <= state47;

num_count <= 20'd2000; lcd_e <= 1'b0; end

state47:begin

state <= state48; num_count <= 20'd4; lcd_rs <= 1'b1; lcd_d <= 4'h4; end

state48:begin

state <= state49;

num_count <= 20'd12; lcd_e <= 1'b1; end

state49:begin

state <= state50;

num_count <= 20'd80; lcd_e <= 1'b0; end

state50:begin

state <= state51; num_count <= 20'd4; lcd_d <= 4'hb; end

state51:begin

state <= state52;

num_count <= 20'd12; lcd_e <= 1'b1; end

state52:begin state <= state53;

num_count <= 20'd2000; lcd_e <= 1'b0; end

state53:begin

state <= state54; num_count <= 20'd4; lcd_rs <= 1'b1; lcd_d <= 4'h2;

end

state54:begin state <= state55;

num_count <= 20'd12; lcd_e <= 1'b1; end state55:begin

state <= state56;

num_count <= 20'd80; lcd_e <= 1'b0; end

state56:begin

state <= state57; num_count <= 20'd4; lcd_d <= 4'h1; end state57:begin

state <= state58;

num_count <= 20'd12; lcd_e <= 1'b1; end state58:begin

state <= state59;

num_count <= 20'd4000; lcd_e <= 1'b0; end

state59:begin

state <= state35;

num_count <= 20'd800; end

default:begin

state <= state1; num_count <= 20'd800; end endcase

endmodule

4、编译成功的程序

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: //

// Create Date: 15:48:30 04/21/2015 // Design Name:

// Module Name: lcd // Project Name: // Target Devices: // Tool versions: // Description: //

// Dependencies: //

// Revision:

// Revision 0.01 - File Created // Additional Comments: //

////////////////////////////////////////////////////////////////////////////////// module lcd(clk,reset,lcd_rs,lcd_rw,lcd_e,lcd_d,flash_ce); input clk; input reset; output lcd_rs; output lcd_rw; output lcd_e;

output [3:0] lcd_d; output flash_ce; reg lcd_rs,lcd_e; reg[3:0] lcd_d; assign flash_ce = 1; assign lcd_rw = 0;

reg [19:0] delay_count; reg [19:0] num_count;

parameter state1 = 6'b000001;

parameter state2 = 6'b000010; parameter state3 = 6'b000011; parameter state4 = 6'b000100; parameter state5 = 6'b000101;

parameter state6 = 6'b000110; parameter state7 = 6'b000111; parameter state8 = 6'b001000; parameter state9 = 6'b001001; parameter state10 = 6'b001010; parameter state11 = 6'b001011; parameter state12 = 6'b001100; parameter state13 = 6'b001101; parameter state14 = 6'b001110; parameter state15 = 6'b001111; parameter state16 = 6'b010000; parameter state17 = 6'b010001; parameter state18 = 6'b010010; parameter state19 = 6'b010011; parameter state20 = 6'b010100; parameter state21 = 6'b010101; parameter state22 = 6'b010110; parameter state23 = 6'b010111; parameter state24 = 6'b011000; parameter state25 = 6'b011001; parameter state26 = 6'b011010; parameter state27 = 6'b011011; parameter state28 = 6'b011100; parameter state29 = 6'b011101; parameter state30 = 6'b011110; parameter state31 = 6'b011111; parameter state32 = 6'b100000; parameter state33 = 6'b100001; parameter state34 = 6'b100010; parameter state35 = 6'b100011; parameter state36 = 6'b100100; parameter state37 = 6'b100101; parameter state38 = 6'b100110; parameter state39 = 6'b100111; parameter state40 = 6'b101000; parameter state41 = 6'b101001; parameter state42 = 6'b101010; parameter state43 = 6'b101011; parameter state44 = 6'b101100; parameter state45 = 6'b101101;

parameter state46 = 6'b101110; parameter state47 = 6'b101111; parameter state48 = 6'b110000; parameter state49 = 6'b110001;

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