基于FPGA的数字系统设计实验3控制液晶显示屏显示字符OK(5)

state6:begin

state <= state7;

num_count <= 20'd5000; lcd_e <= 1'b0; end

state7:begin

state <= state8; num_count <= 20'd4; lcd_d <= 4'h2; end

state8:begin

state <= state9;

num_count <= 20'd12; lcd_e <= 1'b1; end

state9:begin

state <= state10;

num_count <= 20'd4000; lcd_e <= 1'b0; end

//set funtion mode state10:begin

state <= state11;

num_count <= 20'd4; lcd_rs <= 0; lcd_d <= 4'h2; end

state11:begin

state <= state12;

num_count <= 20'd12; lcd_e <= 1'b1; end

state12:begin

state <= state13;

num_count <= 20'd80; lcd_e <= 1'b0; end

state13:begin

state <= state14; num_count <= 20'd4; lcd_d <= 4'h8; end

state14:begin

state <= state15;

num_count <= 20'd12; lcd_e <= 1'b1; end

state15:begin

state <= state16;

num_count <= 20'd4000; lcd_e <= 1'b0; end //set entry mode state16:begin

state <= state17; num_count <= 20'd4; lcd_d <= 4'h0; end

state17:begin

state <= state18;

num_count <= 20'd12; lcd_e <= 1'b1; end

state18:begin

state <= state19;

num_count <= 20'd80; lcd_e <= 1'b0; end

state19:begin

state <= state20; num_count <= 20'd4; lcd_d <= 4'h6; end state20:begin

state <= state21;

num_count <= 20'd12; lcd_e <= 1'b1;

end state21:begin

state <= state22;

num_count <= 20'd4000; lcd_e <= 1'b0; end

//set display on/off

state22:begin state <= state23; num_count <= 20'd4; lcd_d <= 4'h0; end state23:begin

state <= state24;

num_count <= 20'd12; lcd_e <= 1'b1; end state24:begin

state <= state25;

num_count <= 20'd80; lcd_e <= 1'b0; end state25:begin

state <= state26; num_count <= 20'd4; lcd_d <= 4'hc; end

state26:begin state <= state27;

num_count <= 20'd12; lcd_e <= 1'b1; end state27:begin

state <= state28;

num_count <= 20'd4000; lcd_e <= 1'b0; end //clear display

state28:begin state <= state29; num_count <= 20'd4; lcd_d <= 4'h0; end state29:begin

state <= state30;

num_count <= 20'd12; lcd_e <= 1'b1; end state30:begin

state <= state31;

num_count <= 20'd80;

lcd_e <= 1'b0; end state31:begin

state <= state32; num_count <= 20'd4; lcd_d <= 4'h1; end

state32:begin state <= state33;

num_count <= 20'd12; lcd_e <= 1'b1; end state33:begin

state <= state34;

num_count <= 20'd2000; lcd_e <= 1'b0; end state34:begin

state <= state35;

num_count <= 20'd82000; end

//set DD RAM address state35:begin

state <= state36; num_count <= 20'd4; lcd_rs <= 1'b0; lcd_e <= 1'b0; lcd_d <= 4'h8; end

state36:begin

state <= state37;

num_count <= 20'd12; lcd_e <= 1'b1; end

state37:begin

state <= state38;

num_count <= 20'd80; lcd_e <= 1'b0; end

state38:begin state <= state39;

num_count <= 20'd4; lcd_d <= 4'h0; end

state39:begin state <= state40;

num_count <= 20'd12; lcd_e <= 1'b1; end

state40:begin state <= state41;

num_count <= 20'd4000; lcd_e <= 1'b0; end

// now starts writing data to DD RAM state41:begin state <= state42; num_count <= 20'd4; lcd_rs <= 1'b1; lcd_d <= 4'h4; end

state42:begin

state <= state43;

num_count <= 20'd12; lcd_e <= 1'b1; end

state43:begin

state <= state44;

num_count <= 20'd80; lcd_e <= 1'b0; end

state44:begin

state <= state45;

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