基于FPGA的数字系统设计实验3控制液晶显示屏显示字符OK(4)

else

init_state<=five; i <= i + 1; end if;

when six => LCD_E1 <= '0'; init_done <= '0'; if(i = 2000) then init_state<=seven; i <= 0; else

init_state<=six; i <= i + 1; end if;

when seven => SF_D1 <= \LCD_E1 <= '1'; init_done <= '0'; if(i = 11) then init_state<=eight; i <= 0; else

init_state<=seven; i <= i + 1; end if;

when eight => LCD_E1 <= '0'; init_done <= '0'; if(i = 2000) then init_state<=done; i <= 0; else

init_state<=eight; i <= i + 1; end if;

when done => init_state <= done; init_done <= '1'; end case; end if;

end process power_on_initialize; end behavior;

第三种 verilog

该程序实现对 SPARTAN3E 上2x16 LCD 的初始化及各种初始设置，最后输出“OK”字样

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////// // Company: // Engineer: //

// Create Date: 17:43:15 10/03/2009 // Design Name:

// Module Name: lcd_disp_ok // Project Name: // Target Devices: // Tool versions: // Description: //

// Dependencies: //

// Revision:

// Revision 0.01 - File Created // Additional Comments: //

//////////////////////////////////////////////////////////////////////////////////

module lcd_disp_ok(clk,reset,lcd_rs,lcd_rw,lcd_e,lcd_d,flash_ce);

input clk; input reset;

output lcd_rs; output lcd_rw; output lcd_e;

output [3:0] lcd_d; output flash_ce;

reg lcd_rs,lcd_e; reg [3:0] lcd_d;

assign flash_ce = 1; assign lcd_rw = 0;

reg [19:0] delay_count; reg [19:0] num_count;

parameter state1 = 6'b000001;

parameter state2 = 6'b000010; parameter state3 = 6'b000011; parameter state4 = 6'b000100; parameter state5 = 6'b000101; parameter state6 = 6'b000110; parameter state7 = 6'b000111; parameter state8 = 6'b001000; parameter state9 = 6'b001001; parameter state10 = 6'b001010; parameter state11 = 6'b001011; parameter state12 = 6'b001100; parameter state13 = 6'b001101; parameter state14 = 6'b001110; parameter state15 = 6'b001111; parameter state16 = 6'b010000; parameter state17 = 6'b010001; parameter state18 = 6'b010010; parameter state19 = 6'b010011; parameter state20 = 6'b010100; parameter state21 = 6'b010101; parameter state22 = 6'b010110; parameter state23 = 6'b010111; parameter state24 = 6'b011000; parameter state25 = 6'b011001; parameter state26 = 6'b011010; parameter state27 = 6'b011011; parameter state28 = 6'b011100; parameter state29 = 6'b011101; parameter state30 = 6'b011110; parameter state31 = 6'b011111; parameter state32 = 6'b100000; parameter state33 = 6'b100001; parameter state34 = 6'b100010; parameter state35 = 6'b100011; parameter state36 = 6'b100100; parameter state37 = 6'b100101; parameter state38 = 6'b100110;

parameter state39 = 6'b100111; parameter state40 = 6'b101000; parameter state41 = 6'b101001; parameter state42 = 6'b101010; parameter state43 = 6'b101011; parameter state44 = 6'b101100; parameter state45 = 6'b101101;

parameter state46 = 6'b101110; parameter state47 = 6'b101111; parameter state48 = 6'b110000; parameter state49 = 6'b110001; parameter state50 = 6'b110010; parameter state51 = 6'b110011; parameter state52 = 6'b110100; parameter state53 = 6'b110101; parameter state54 = 6'b110110; parameter state55 = 6'b110111; parameter state56 = 6'b111000; parameter state57 = 6'b111001; parameter state58 = 6'b111010; parameter state59 = 6'b111011;

reg [5:0] state; reg state_change;

always @(posedge clk or posedge reset) if(reset) begin

state_change <= 1'b0; delay_count <= 1'b1; end else

if(delay_count == num_count - 1) begin

state_change <= 1'b1; delay_count <= 1'b1; end else

begin

state_change <= 1'b0;

delay_count <= delay_count + 1'b1;

end

always @(posedge state_change or posedge reset) if(reset) begin

state <= state1;

num_count <= 20'd750000;

end else

case(state)

state1:begin

state <= state2; num_count <= 20'd4;

lcd_rs <= 1'b0; lcd_e <= 1'b0; lcd_d <= 4'h3; end

state2:begin

state <= state3;

num_count <= 20'd12; lcd_e <= 1'b1; end

state3:begin

state <= state4;

num_count <= 20'd205000; lcd_e <= 1'b0; end

state4:begin

state <= state5;

num_count <= 20'd4; lcd_d <= 4'h3; end

state5:begin

state <= state6;

num_count <= 20'd12; lcd_e <= 1'b1; end

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