IDT70T3589S-133BFI中文资料(7)

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Truth Table I—Read/Write and Enable Control (1,2,3,4)

OEXXXXXXXXXXLLLLLLLHX

CLK↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑↑X

CE1CE0BE3HXXXLLLLLLLLLLLLLLLXX

LHHHHHHHHHHHHHHHXX

XHHHHLHLLHHHLHLLXX

BE2XXHHHLHHLLHHLHHLLXX

BE1XXHHLHHLHLHLHHLHLXX

BE0

X

XHLHHHLHLLHHHLHLXX

R/WXXXLLLLLLLHHHHHHHXX

ZZLLLLLLLLLLLLLLLLLLH

Byte 3I/O27-35High-ZHigh-ZHigh-ZHigh-ZHigh-ZHigh-ZDINHigh-ZDINDINHigh-ZHigh-ZHigh-ZDOUTHigh-ZDOUTDOUTHigh-ZHigh-Z

Byte 2I/O18-26High-ZHigh-ZHigh-ZHigh-ZHigh-ZDINHigh-ZHigh-ZDINDINHigh-ZHigh-ZDOUTHigh-ZHigh-ZDOUTDOUTHigh-ZHigh-Z

Byte 1I/O9-17High-ZHigh-ZHigh-ZHigh-ZDINHigh-ZHigh-ZDINHigh-ZDINHigh-ZDOUTHigh-ZHigh-ZDOUTHigh-ZDOUTHigh-ZHigh-Z

Byte 0I/O0-8High-ZHigh-ZHigh-ZDINHigh-ZHigh-ZHigh-ZDINHigh-ZDINDOUTHigh-ZHigh-ZHigh-ZDOUTHigh-ZDOUTHigh-Z

MODE

Deselected–Power DownDeselected–Power DownAllBytesDeselectedWrite to Byte 0 OnlyWrite to Byte 1 OnlyWrite to Byte 2 OnlyWrite to Byte 3 OnlyWrite to Lower 2 Bytes Only Write to Upper 2 bytes OnlyWrite to All BytesRead Byte 0 OnlyRead Byte 1 OnlyRead Byte 2 OnlyRead Byte 3 OnlyRead Lower 2 Bytes OnlyRead Upper 2 Bytes OnlyRead All BytesOutputsDisabled

High-ZSleepMode

5666 tbl 02

NOTES:

1."H" = VIH, "L" = VIL, "X" = Don't Care.2.ADS, CNTEN, REPEAT = VIH.

3.OE and ZZ are asynchronous input signals.

4.It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.

Truth Table II—Address Counter Control (1,2)

AddressAnXXX

PreviousInternalAddressXAnAn + 1X

InternalAddressUsedAnAn+1An + 1An

CLK↑↑↑↑

ADS L(4)HHX

CNTENXL(5)HX

REPEAT(6)

HHHL(4)

I/O(3)DI/O (n)DI/O(n+1)DI/O(n+1)DI/O(n)

External Address Used

Counter Enabled—Internal Address generation

External Address Blocked—Counter disabled (An + 1 reused)Counter Set to last valid ADS load

5666 tbl 03

MODE

NOTES:

1."H" = VIH, "L" = VIL, "X" = Don't Care.

2.Read and write operations are controlled by the appropriate setting of R/W, CE0, CE1, BEn and OE.

3.Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.4.ADS and REPEAT are independent of all other memory control signals including CE0, CE1 and BEn

5.The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other memory control signals including CE0, CE1, BEn.

6.When REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded

via ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.

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