IDT70T3589S-133BFI中文资料

元器件交易网http://www.77cn.com.cn

HIGH-SPEED 2.5V256/128/64K x 36

IDT70T3519/99/89SSYNCHRONOUS

DUAL-PORT STATIC RAM

Features:

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True Dual-Port memory cells which allow simultaneousaccess of the same memory locationHigh-speed data access

–Commercial: 3.4 (200MHz)/3.6ns (166MHz)/

4.2ns (133MHz)(max.)

–Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)Selectable Pipelined or Flow-Through output modeCounter enable and repeat features

Dual chip enables allow for depth expansion withoutadditional logic

Interrupt and Collision Detection FlagsFull synchronous operation on both ports

–5ns cycle time, 200MHz operation (14Gbps bandwidth)–Fast 3.4ns clock to data out

–1.5ns setup to clock and 0.5ns hold on all control, data, andaddress inputs @ 200MHz

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–Data input, address, byte enable and control registers–Self-timed write allows fast cycle time

Separate byte controls for multiplexed bus and busmatching compatibility

Dual Cycle Deselect (DCD) for Pipelined Output Mode2.5V (±100mV) power supply for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V(±100mV) power supply for I/Os and control signals on

each port

Industrial temperature range (-40°C to +85°C) isavailable at 166MHz and 133MHz

Available in a 256-pin Ball Grid Array (BGA), a 208-pinPlastic Quad Flatpack (PQFP) and 208-pin fine pitch BallGrid Array (fpBGA)

Supports JTAG features compliant with IEEE 1149.1

Due to limited pin count JTAG is not supported on the 208-pin PQFP package

ZZNOTES:

1.Address A17 is a NC for the IDT70T3599. Also, Addresses A17 and A16 are NC's for the IDT70T3589.

2.The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. All static inputs, i.e., PL/FTx and OPTxR

(2)

5666drw01

APRIL 2004

DSC 5666/6

©2004 Integrated Device Technology, Inc.

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