24小时制时钟—EDA课程设计报告(4)

石家庄铁道大学

数字钟设计与制作

16

BEGIN

CASE A IS WHEN \ WHEN \ WHEN \

WHEN \WHEN \WHEN \WHEN \WHEN \WHEN \WHEN \

WHEN OTHERS =>NULL; END CASE;

END PROCESS P3; END behave;

（5）具整点报时程序

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL;

ENTITY baoshi IS PORT(CLK :IN STD_LOGIC; FENZHONG : IN STD_LOGIC_VECTOR(5 DOWNTO 0);

XIAOSHI : IN STD_LOGIC_VECTOR(4 DOWNTO 0); CQ : OUT STD_LOGIC);

END;

ARCHITECTURE behav OF baoshi IS

BEGIN

PROCESS(CLK)

VARIABLE FENBIAN :STD_LOGIC_VECTOR(10 DOWNTO 0); VARIABLE EN :STD_LOGIC;

BEGIN

FENBIAN(0):=FENBIAN(0);

FENBIAN(1):=FENBIAN(1); FENBIAN(2):=FENBIAN(2); FENBIAN(3):=FENBIAN(3); FENBIAN(4):=FENBIAN(4); FENBIAN(5):=FENBIAN(5); FENBIAN(6):=XIAOSHI(0); FENBIAN(7):=XIAOSHI(1); FENBIAN(8):=XIAOSHI(2);

石家庄铁道大学

数字钟设计与制作

17

FENBIAN(9):=XIAOSHI(3);

FENBIAN(10):=XIAOSHI(4); CASE FENBIAN IS WHEN \ WHEN OTHERS => EN :='0'; END CASE;

IF EN='1' THEN CQ<=CLK; END IF;

END PROCESS; END behav;

思路二实现：

（1）非压缩BCD码的24、59进制程序

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity Minute is port(clk:in std_logic; clk2:in std_logic; tiao:in std_logic;

clr:in std_logic;

qh,ql:out std_logic_vector(3 downto 0); co:out std_logic );end;

architecture a of Minute is

signal zqh,zql:std_logic_vector(3 downto 0); signal clk_temp: std_logic; begin

process(clk,clk2,tiao,clk_temp) variable co_temp: std_logic;

石家庄铁道大学 数字钟设计与制作

18

begin

if tiao='1' then clk_temp<=clk2; co<='0'; else

clk_temp<=clk; co<=co_temp; end if; if clr='1' then zqh<=\ zql<=\ co<='0';

elsif clk_temp'event and clk_temp='1' then if zqh=\ zqh<=\ zql<=\ co_temp:='1'; elsif zql=\ zql<=\ else zql<=zql+1; co_temp:='0'; end if; end if; end process; qh<=zqh; ql<=zql; end;

石家庄铁道大学

数字钟设计与制作

19

（2）动态扫描程序

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity scan is

port( clk: in std_logic;

sh: in std_logic_vector(3 downto 0); sl: in std_logic_vector(3 downto 0); mh: in std_logic_vector(3 downto 0); ml: in std_logic_vector(3 downto 0); hh: in std_logic_vector(3 downto 0); hl: in std_logic_vector(3 downto 0); leda:out std_logic;

xuan0:out std_logic; xuan1:out std_logic; xuan2:out std_logic; xuan3:out std_logic; xuan4:out std_logic; xuan5:out std_logic

ledb:out std_logic; ledc:out std_logic; ledd:out std_logic; lede:out std_logic; ledf:out std_logic; ledg:out std_logic;

石家庄铁道大学

数字钟设计与制作

20

); end scan;

architecture behvd of scan is

SIGNAL xuan: std_logic_vector(5 downto 0); signal qtemp: std_logic_vector(2 downto 0); signal num: std_logic_vector(3 downto 0); signal led: std_logic_vector(6 downto 0); begin

p1:process (clk) begin

if (clk'event and clk= '0') then if( qtemp < 5) then qtemp <=qtemp+1; else

qtemp <= \ end if; end if;

end process;

p2:PROCESS(qtemp,sh,sl,mh,ml,hh,hl) begin

case qtemp is

when \ when \ when \

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