AS - 001基于FPGA的HDB3编译码的建模与实现 - 图文(8)

基于FPGA的HDB3编译码的建模与实现 附录二

附录二 HDB3码译码器完整源程序

--0表示没有,1表示有1个 LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY DEHDB3 IS

PORT(HDB3_DATA: IN STD_LOGIC_VECTOR(1 DOWNTO 0); CLK: IN STD_LOGIC; CLR: IN STD_LOGIC; DEHDB3: OUT STD_LOGIC); END ENTITY DEHDB3;

ARCHITECTURE BEHAV OF DEHDB3 IS

SIGNAL REG0,REG1,REG2,REG3,REG4: STD_LOGIC;

SIGNAL COUNT01: INTEGER RANGE 1 DOWNTO 0; SIGNAL COUNT10: INTEGER RANGE 1 DOWNTO 0; BEGIN

PROCESS(CLK,CLR) BEGIN

IF(CLK'EVENT AND CLK='1')THEN IF(CLR='1')THEN COUNT01<=0; COUNT10<=0; REG0<='0'; REG1<='0'; REG2<='0'; REG3<='0'; REG4<='0';

ELSE IF(HDB3_DATA=\ --+1 IF(COUNT01=1)THEN --10>-1 COUNT01<=0; COUNT10<=0; REG0<='0'; REG1<='0'; REG2<='0'; REG3<='0'; REG4<=REG3; ELSE

COUNT01<=1; COUNT10<=0; REG0<='1';

34

--1>HIGH,0>LOW --+1 ---1 UOH UOH 基于FPGA的HDB3编译码的建模与实现 附录二

REG1<=REG0; REG2<=REG1; REG3<=REG2;

REG4<=REG3; --V END IF;

ELSIF(HDB3_DATA=\ ---1 IF(COUNT10=1)THEN COUNT01<=0; COUNT10<=0; REG0<='0'; REG1<='0'; REG2<='0'; REG3<='0';

REG4<=REG3; ELSE

COUNT01<=0; COUNT10<=1; REG0<='1'; REG1<=REG0; REG2<=REG1; REG3<=REG2;

REG4<=REG3; END IF; ELSE

COUNT01<=COUNT01; COUNT10<=COUNT10; REG0<='0'; REG1<=REG0; REG2<=REG1; REG3<=REG2; REG4<=REG3; END IF; END IF; END IF; END PROCESS; DEHDB3<=REG4;

END ARCHITECTURE BEHAV;

--V ---1 35

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