AS - 001基于FPGA的HDB3编译码的建模与实现 - 图文

基于FPGA的HDB3编译码的建模与实现

吴英发

（吉首大学物理科学与信息工程学院，湖南 吉首 416000）

摘 要

本文以FPGA为硬件平台，基于EDA工具QUARTUSⅡ为软件平台上对HDB3编/译码进行实现。由于在EDA的软件平台QUARTUSⅡ上不能处理双极性的信号，因此对HDB3码的编/译码的实现分为：软件部分和硬件部分。软件部分是基于QUARTUSⅡ的平台上对输入的码元进行编码和译码，通过系统仿真，验证了HDB3码的编译码的正确性；硬件部分采用CD74HC4052双四选一的数模选择器实现单极性到双极性的转换；采用AD790和SE5539实现双极性到单极性的转换。最后，通过仿真，验证了方案的正确性。

关键词：HDB3；建模；VHDL；编/译码；QUARTUSⅡ

The Modeling and Realization of the HDB3 Encoding and

Decoding Based on FPGA

Wu Yingfa

(College of Physics Science and Information Engineering,Jishou University,Jishou,Hunan 416000)

Abstract

The HDB3 encoding and decoding are realized based on taking FPGA as hardware platform and taking QUARTUSⅡ，a kind of EDA tool，as the software platform. Because QUARTUSⅡ can not deal with the bipolar of signal，the realization of HDB3’s encoding/decoding function is divided into two parts: software and hardware part. In the software part: the encoding/decoding of HDB3 are realized based on QUARTUSⅡ, and the simulation result that the realization is correct. In the hardware part: the CD74HC4052 are used to realize unipolar /bipolar transformation, at the same time, the AD790 and SE5539 are used to realize bipolar/unipolar transformation. At last, the efficiency of the above method is proved by the simulation results.

Key words： HDB3；Modeling；VHDL；Encoding/Decoding；QUARTUSⅡ

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目 录

第一章 绪 论 ······················································································································ 1 第二章 EDA辅助设计工具的介绍 ·················································································· 3 2.1 FPGA的介绍 ············································································································· 3 2.1.1 PLD的介绍 ······································································································· 3 2.1.2 FPGA的系统介绍 ···························································································· 3 2.2 VHDL语言和QUARTUSⅡ ···················································································· 4 2.2.1 VHDL语言 ········································································································ 4 2.2.2 EDA工具QUARTUSⅡ ··················································································· 5 第三章 HDB3码编码器的建模与实现 ············································································ 6 3.1 HDB3码的编码规则 ································································································· 6 3.2 基于VHDL的编码器的建模及实现 ···································································· 6 3.2.1 编码器的VHDL建模及难点分析 ································································· 7 3.2.2 基于VHDL编码器的实现 ············································································· 7 3.3编码中单/双极性转换的实现 ················································································ 12 3.3.1单/双极性转换的流程图 ··············································································· 12 3.3.2单/双极性变换的VHDL实现 ······································································ 14 3.3.3单/双极性变换的硬件实现 ··········································································· 15 3.4 HDB3码编码器的波形仿真及分析 ······································································ 17 3.5 小结 ························································································································· 18 第四章 HDB3码译码器的建模与实现 ·········································································· 19 4.1 HDB3码的译码规则及建模 ·················································································· 19 4.2 译码中双/单极性的实现 ······················································································· 19 4.3 基于VHDL译码器的实现 ···················································································· 20 4.3.1基于VHDL译码器的流程图 ········································································ 20 4.3.2 HDB3码译码器的程序设计 ·········································································· 20 4.4 HDB3码译码器的波形仿真及分析 ······································································ 23 4.5 小结 ························································································································· 24 第五章 结束语 ·················································································································· 26 参考文献 ···························································································································· 26 致谢 ···································································································································· 26 附录一 ································································································································ 29 附录二 ································································································································ 34

基于FPGA的HDB3编译码的建模与实现 绪论

第一章 绪 论

数字基带信号的传输是数字通信系统的重要组成部分之一。特别是HDB3(High Density Bipolar-3 Coding，三阶高密度双极性码)码的使用，其不但保持AMI(Alternation mark Inversion，交替反转码)码的优点外，更使连0串的个数减到至多0个的优点，而且还克服了AMI码的关于可能出现长连0串而造成提取定时信号困难的缺点。基于上述的特点HDB3码在通信传输领域应用很广泛，因此其作为CCITT推荐使用的码型之一[1]。

本毕业设计是采用EDA工具实现HDB3码的仿真和校验，从而使系统的实现具有很大的灵活性。EDA(Electronics Design Automation，电子设计自动化)就是以大规模可编程逻辑器件为设计载体，以硬件描述语言为系统逻辑描述的主要表达方式，以计算机、大规模可编程逻辑器件的开发软件及实验开发系统为设计工具，通过有关的开发软件，自动完成用软件方式设计的电子系统到硬件系统的编辑逻辑、逻辑化简、逻辑分割、逻辑综合及优化、逻辑布局布线、逻辑仿真，直至对于特定芯片的适配编译、逻辑映射、编程下载等工作，最终形成集成电子系统[2.4]。

本毕业设计的主要工作是HDB3码的编译码的建模与实现，对于HDB3编译码模块，一般以硬件的方式来实现的。但它具有产品更新慢、设计灵活性差、不可重配置及现场升级性能缺乏等缺点。因此拟采用可编程逻辑电路来实现。可编程逻辑电路是EDA的一个重要技术基础，主要包括FPGA(Field Programmable Gate Array，现场可编程逻辑门阵列)和CPLD(Complex Programmable Logic Devices，复杂可编程逻辑器件)，它们具有丰富的可重配置逻辑资源，既包含有大量实现组合逻辑的资源；还包含有相当数量的触发器，因此采用EDA技术进行电子系统的设计有以下优点：

? 系统可现场编程，在线升级； ? 用软件的方式设计硬件；

? 整个系统可集成在一个芯片上，体积小、功耗低、可靠性高；

? 用软件方式设计的硬件系统的转换是由有关的开发软件自动完成，降低了系统设计的难度。

对于HDB3编译码器的实现，本毕业设计采用硬件描述语言VHDL来实现。用VHDL语言设计分别设计一个完善的HDB3码编码器和译码器。本设计是从HDB3原理出发，采用“从顶到底(TOP-DOWN)”设计方法，以EDA工具QUARTUSⅡ5.1为软件平台，输入HDB3的代码并对其进行编译、综合和仿真，经过功能测试、验证，最终实现基于FPGA的HDB3码的编码和译码功能。

本文对章节的安排如下：

第二章对FPGA、VHDL（Very-High-Speed Integrated Circuit Hardware Description

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基于FPGA的HDB3编译码的建模与实现 绪论

Language，甚高速硬件描述性语言）和QUARTUSⅡ等进行简介，并选定FPGA和QUARTUSⅡ作为系统的开发环境。

第三章介绍HDB3码的编码原理，并基于FPGA对HDB3码编码部分进行建模及实现，通过波形仿真，校验编码模块的正确性。

第四章介绍HDB3码的译码原理，并基于FPGA对HDB3码译码部分进行建模及实现，通过波形仿真，校验译码模块的正确性。

第五章对全文进行总结。

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基于FPGA的HDB3编译码的建模与实现 EDA辅助设计工具的介绍

第二章 EDA辅助设计工具的介绍

2.1 FPGA的介绍

2.1.1 PLD的介绍[2.4]

PLD（Programmable Logic Devices，可编程逻辑器件）是一种由用户编程以实现某种逻辑功能的新型逻辑器件。它诞生于20世纪70年代，在20世纪80年代以后，随着集成电路技术和计算机技术的发展而迅速发展。自问世以来，PLD经历了从PROM(Programmable Read-Only Memory，可编程序的只读存储器)、PLA(Programmable Logic Array，可编程序逻辑阵列)、PAL（Programmable Array Logic，可编程阵列逻辑）、GAL(Generic Array Logic，通用阵列逻辑)到FPGA、ispLSI(in system programmable Large Scale Integration，在系统可编程大规模集成电路)等高密度PLD的发展过程。在此期间，PLD的集成度、速度不断提高，功能不断增强，结构趋于更合理，使用起来灵活方便。PLD的出现，打破了由中小规模通用型集成电路和大规模专用集成电路；垄断的局面。与中小型规模通用型集成电路相比，用PLD实现数字系统，有集成度高、速度快、功耗小、可靠性高等优点。与大规模专用集成电路相比，用PLD实现数字系统，有研制周期短、先期投资少、无风险、修改逻辑设计方便、小批量生产成本低等优势。

最早的可编程逻辑器件出现在20世纪70年代初，主要是PROM和PAL。随后出现了PAL、GAL、EPLD(Erasable Programmable Logic Devices，可擦除可编程逻辑器件)和CPLD、PFGA、ispLSI。 2.1.2 FPGA的系统介绍

FPGA是20世纪80年代中期，美国Altera公司推出一种现场可编程门阵列，其结构主要分为三部分：可编程逻辑单元，可编程输入输出单元和可编程连线部分。FPGA器件采用逻辑单元阵列结构和静态随机存取存储器工艺，设计灵活，集成度高，可利用计算机辅助设计，绘出实现用户逻辑原理图、编辑布尔方程或用硬件描述语言等方式设计输入；然后经一系列转换程序、自动布局布线、模拟仿真的过程；最后生成配置FPGA器件的数据文件，对FPGA器件初始化。这样实现了满足用户要求的专用集成电路，真正达到了用户自行设计、自行研制和自行生产集成电路的目的。

概括来说，FPGA器件具有下列优点：高密度、高效率、系列化、标准化、小型化、多功能、低功耗、低成本、设计灵活方便，可无限次反复编程，并可现场

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