SKEA128PB(3)

Timer????Operation in Wait or Stop modes for lower noise operationAsynchronous clock source for lower noise operationSelectable asynchronous hardware conversion trigger

Automatic compare with interrupt for less-than, or greater-than or equal-to, programmable value

4.5.4.2

??????

Analog Comparator (ACMP)

The ACMP module has the following features.

Operational over the whole supply range of 2.7–5.5 V

On-chip 6-bit resolution DAC with selectable reference voltage from VDD or internal bandgapConfigurable hysteresis

Selectable interrupt on rising-edge, falling-edge, or both rising or falling edges of the comparator outputSelectable inversion on comparator output

Up to four selectable comparator inputs; one of these is fixed and connected to built-in DAC output while the others areexternally mapped on pinouts.?Operational in Stop mode

4.5.5Timer

4.5.5.1

????????????

FlexTimers (FTM)

The FlexTimer module exhibits the following features.

Selectable FTM source clock, supporting separate timer clock from core and bus, up to 48 MHzProgrammable prescaler

16-bit counter supporting free-running or initial/final value, and counting is up or up-downInput capture, output compare, and edge-aligned and center-aligned PWM modesInput capture and output compare modes

Operation of FTM channels as pairs with equal outputs, pairs with complimentary outputs, or independent channelswith independent outputs

Deadtime insertion is available for each complementary pairGeneration of hardware triggersSoftware control of PWM outputs

Up to four fault inputs for global fault controlConfigurable channel polarity

Programmable interrupt on input capture, reference compare, overflowed counter, or detected fault condition

4.5.5.2

????

Periodic Interrupt Timer (PIT)

The features of the PIT module are given below.

Two general-purpose interrupt timers

One interrupt timer for triggering ADC conversions32-bit counter resolution

Clocked by bus clock frequency

4.5.5.3Real-Time Clock (RTC)

Following are the features of the real-time clock.?16-bit up-counter

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Communication interfaces?16-bit modulo match limit

?Software controllable periodic interrupt on match

?Software selectable clock sources for input to prescaler with programmable 16 bit prescaler

?OSC 32.768 kHz nominal?LPO (~1 kHz)?Bus clock

?Internal reference clock

4.5.5.4

The pulse width timer (PWT) includes the following features:

?Automatic measurement of pulse width with 16 bit resolution?Separate positive and negative pulse width measurements?Programmable triggering edge for starting measurement

?Programmable measuring time between successive alternating edges, rising edges or falling edges?Programmable prescaler from clock input as 16 bit counter time base

?Two selectable clock sources, supporting separate timer clock up to 48 MHz?Four selectable pulse inputs

?Programmable interrupt generation upon pulse width value updated and counter overflow

Pulse Width Timer (PWT)

4.5.6Communication interfaces

4.5.6.1

???????????

Inter-Integrated Circuit (I2C)

The features of the I2C module are as follows.

Compatible with I2C bus standard

Up to 100 kbit/s with maximum bus loadingMultimaster operation

Software programmable for one of 64 different serial clock frequenciesProgrammable slave address and glitch input filterInterrupt-driven byte-by-byte data transfer

Arbitration lost interrupt with automatic mode switching from master to slaveCalling address identification interrupt

Bus busy detection broadcast and 10-bit address extension

Address matching causes wake-up when processor is in low-power mode.I2C0 supports 4-wire interface

4.5.6.2

????

Universal Asynchronous Receiver/Transmitter (UART)

The UART module has the following features.

Full-duplex, standard non-return-to-zero (NRZ) format

Double-buffered transmitter and receiver with separate enablesProgrammable baud rates (13-bit modulo divider)Interrupt-driven or polled operation:

?Transmit data register empty and transmission complete?Receive data register full

?Receive overrun, parity error, framing error, and noise error?Idle receiver detect

?Active edge on receive pin?Break detect supporting LIN

?Hardware parity generation and checking

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PreliminaryFreescale Semiconductor, Inc.

Human machine interface?????Programmable 8-bit or 9-bit character lengthProgrammable 1-bit or 2-bit stop bits

Receiver wake-up by idle-line or address-mark

Optional 13-bit break character generation / 11-bit break character detectionSelectable transmitter output polarity

4.5.6.3

??????????

Serial Peripheral Interface (SPI)

The features of the SPI module are listed below.

Master and slave mode

Full-duplex, three-wire synchronous transfersProgrammable transmit bit rate

Double-buffered transmit and receive data registersSerial clock phase and polarity optionsSlave select output

Mode fault error flag with CPU interrupt capabilityControl of SPI operation during Wait modeSelectable MSB-first or LSB-first shiftingReceive data buffer hardware match feature

4.5.6.4Freescale's scalable controller area network (MSCAN)

The features of the MSCAN module are listed below.

?Implementation of the CAN protocol - Version 2.0A/B

?Standard and extended data frames

?Zero to eight bytes data length Introduction?Programmable bit rate up to 1 Mbps1?Support for remote frames

?Five receive buffers with FIFO storage scheme

?Three transmit buffers with internal prioritization using a \

?Flexible maskable identifier filter supports two full-size (32-bit) extended identifier filters, or four 16-bit filters, oreight 8-bit filters

?Programmable wake-up functionality with integrated low-pass filter?Programmable loopback mode supports self-test operation?Programmable listen-only mode for monitoring of CAN bus?Programmable bus-off recovery functionality

?Separate signalling and interrupt capabilities for all CAN receiver and transmitter error states (warning, error passive,bus-off)

?Programmable MSCAN clock source either bus clock or oscillator clock?Internal timer for time-stamping of received and transmitted messages?Three low-power modes: sleep, power down, and MSCAN enable?Global initialization of configuration registers

4.5.7Human machine interface

4.5.7.1

General-Purpose Input/Output (GPIO)

The features of the GPIO module are listed below.

1.Depending on the actual bit timing and the clock jitter of the clock source.

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Human machine interface????Hysteresis and configurable pull up device on all input pinsConfigurable drive strength on some output pins

Independent pin value register to read logic level on digital pinFast IO access in single-cycle core clock

4.5.7.2Keyboard Interrupts (KBI)

The KBI features include:

?Up to eight keyboard interrupt pins with individual pin enable bits?Each keyboard interrupt pin is programmable as:

?falling-edge sensitivity only?rising-edge sensitivity only

?both falling-edge and low-level sensitivity?both rising-edge and high-level sensitivity?One software-enabled keyboard interrupt?Exit from low-power modes

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PreliminaryFreescale Semiconductor, Inc.

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freescale.com/supportInformation in this document is provided solely to enable system andsoftware implementers to use Freescale products. There are no expressor implied copyright licenses granted hereunder to design or fabricateany integrated circuits based on the information in this document.

Freescale reserves the right to make changes without further notice toany products herein.

Freescale makes no warranty, representation, or guarantee regardingthe suitability of its products for any particular purpose, nor doesFreescale assume any liability arising out of the application or use ofany product or circuit, and specifically disclaims any and all liability,including without limitation consequential or incidental damages.“Typical” parameters that may be provided in Freescale data sheetsand/or specifications can and do vary in different applications, andactual performance may vary over time. All operating parameters,

including “typicals,” must be validated for each customer application bycustomer's technical experts. Freescale does not convey any licenseunder its patent rights nor the rights of others. Freescale sells productspursuant to standard terms and conditions of sale, which can be foundat the following address: freescale.com/SalesTermsandConditions.Freescale, the Freescale logo, and Kinetis are trademarks of FreescaleSemiconductor, Inc., Reg. U.S. Pat. & Tm. Off. All other product orservice names are the property of their respective owners. ARM andCortex-M0+ are the registered trademarks of ARM Limited.?2013-2014 Freescale Semiconductor, Inc.

Document Number SKEA128PB

Revision 1.1, 02/2014

Preliminary

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