FeaturesTable 2.KEA128 family summaryPerformance (MHz)Memory64 QFP (10x10)Flash (KB)Package80 LQFP(14x14)++Sub-FamilyKEA1284864128SRAM(KB)816++4.3Part numbers and packaging
Q KEA A C FFF M T PP (N)
Qualification status
Tape and Reel (T&R)
FamilyKey attributeCAN available
Flash size
Package identifier
Temperature range (°C)Maskset revision
Figure 2. Part numbers diagramsTable 3.Part number field descriptionFieldQKEAACFFFMTPPNQualification statusKinetis E automotive familyKey attributeCAN availabilityProgram flash memory sizeMaskset revisionTemperature range (°C)Package identifierPackaging typeDescriptionValues?S = Automotive Qualified?P = Prequalification?KEA?Z = Cortex-M0+?N = CAN not available?(Blank) = CAN available?64 = 64 KB?128 = 128 KB?F0 = 1st Fab version?F1 = Revision after 1st version?M = –40 to 125?LH = 64 LQFP (10 mm x 10 mm)?LK = 80 LQFP (14 mm x 14 mm)?R = Tape and reel?(Blank) = TraysProduct Brief, Rev 1.1, 02/2014
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PreliminaryFreescale Semiconductor, Inc.
Features4.4KEA128 family features
The following sections list the differences among the various devices available within the KEA128 family.The features listed below each part number specify the maximum configuration available on that device. The signalmultiplexing configuration determines which modules can be used simultaneously.
4.4.1KEA128 family features (48 MHz performance)
The following table lists the differences among the various devices available within the KEA128 family. The features listedbelow each part number specify the maximum configuration available on that device. The signal multiplexing configurationdetermines which modules can be used simultaneously.
Table 4.KEA128 48 MHz performance tableSKEAZ128AMLH(R)SKEAZ128AMLK(R)48 MHz80LQFP128 KB16 KB--YES-YESYES-YESFLLYESYESYESSKEAZ64AMLH(R)SKEAZ64AMLK(R)48 MHz80LQFP64 KB8 KB--YES-YESYES-YESFLLYESYESYESSC part numberGeneralCPU frequencyPin countPackageFlashSRAMEEPROMROMDebug-SWDMTBWatchdog /w ind. clockPMCDMABME (bit manipulation engine)ICSMain OSC (32 kHz, 4-20 MHz)IRC (~32 kHz)LPO (~1 kHz)48 MHz64LQFPMemories and memory interfaces64 KB8 KB--Core modulesYES-System modulesYESYES-YESClock modulesFLLYESYESYESTable continues on the next page...FLLYESYESYESYESYES-YESYES-128 KB16 KB--48 MHz64LQFPProduct Brief, Rev 1.1, 02/2014
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FeaturesTable 4.KEA128 48 MHz performance table (continued)SKEAZ128AMLH(R)SKEAZ128AMLK(R)1YES12bit, 1x16ch221121x2ch132-21--71822.7-5.5 V2.7 V-40 to 125 °CSKEAZ64AMLH(R)SKEAZ64AMLK(R)1YES12bit, 1x16ch221121x2ch132-21--71822.7-5.5 V2.7 V-40 to 125 °CSC part number16-bit RTCCRCADC with 8 buffer entry6-bit DACACMPBandgap Vref (no pin-out)16-bit FTM (6-ch)16-bit FTM (2-ch)PIT (32-bit)PWTUART (LIN slave capable)SPI (8-bit)SPI (16-bit )I2C (400 kb/s)CANSegment LCDTSI (capacitive touch)Total GPIOs20 mA high-drive GPIOTrue open-drainVoltage rangeFlash write VTemperature range1Security and integrityYESAnalog12bit, 1x16ch221Timers121x2ch1Communication interfaces32-21Human-machine interface--5882Operating characteristics2.7-5.5 V2.7 V-40 to 125 °C1YES12bit, 1x16ch221121x2ch132-21--58822.7-5.5 V2.7 V-40 to 125 °C4.5Module-by-module feature list
The following sections describe the high-level module features for the family's superset device. See KEA128 family features(48 MHz performance) for differences among the subset devices.
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PreliminaryFreescale Semiconductor, Inc.
Core modules4.5.1Core modules
4.5.1.1
?Up to 48 MHz core frequency from 2.7 V to 5.5 V across temperature range of –40 °C to 125 °C?Supports up to 32 interrupt request sources
?2-stage pipeline microarchitecture for reduced power consumption and improved architectural performance (cycles perinstruction)
?Binary compatible instruction set architecture with the Cortex-M0 core?Thumb instruction set combines high code density with 32-bit performance?Serial wire debug (SWD) reduces the number of pins required for debugging?Single cycle 32 bits by 32 bits multiply
ARM Cortex-M0+ core
4.5.1.2Nested Vectored Interrupt Controller (NVIC)
Following are the features of the NVIC module.?Up to 32 interrupt sources
?Includes a single non-maskable interrupt
4.5.1.3Asynchronous Wake-up Interrupt Controller (AWIC)
The features of the AWIC module are given below.
?Supports interrupt handling when system clocking is disabled in low-power modes
?Takes over and emulates the NVIC behavior when correctly primed by the NVIC on entry to very deep sleep mode.?A rudimentary interrupt masking system with no prioritization logic signals for wake-up as soon as a non-maskedinterrupt is detected
?Contains no programmer’s model visible state and is therefore invisible to end users of the device other than throughthe benefits of reduced power consumption while sleeping
4.5.1.4
?2-pin serial wire debug (SWD) provides external debugger interface
Debug controller
4.5.2System modules
4.5.2.1
?????????
Power Management Control (PMC) unit
The features of the PMC module are listed below.
Separate digital (regulated) and analog (referenced to digital) supply outputsProgrammable power saving modes
No output supply decoupling capacitors required
Available wake-up from power saving modes via RTC and external inputsIntegrated power-on-reset (POR)
Integrated low voltage detect (LVD) with reset (brownout) capabilitySelectable LVD trip points
Programmable low-voltage warning (LVW) interrupt capabilityBuffered bandgap reference voltage output
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Memories and memory interfaces?Factory programmed trim for bandgap and LVD?1 kHz low-power oscillator (LPO)
4.5.2.2Watchdog (WDOG) module
The features of the Watchdog module are described as follows.?Independent clock source input (independent from CPU/bus clock)?Choice between clock sources
?1 kHz internal low-power oscillator (LPOCLK)?Internal 32 kHz reference clock (ICSIRCLK)?External clock (OSCERCLK)?Bus clock
4.5.2.3System clocks
The following clock sources can be used as system clocks.
?System oscillator (OSC)—Loop-control pierce oscillator; crystal or ceramic resonator range of 31.25 to 39.0625 kHz(low-range mode) or 4-24 MHz (high-range mode)?Internal clock source (ICS)
?Frequency-locked loop (FLL) controlled by internal or external reference
?40 MHz~50 MHz FLL output
?Internal reference clocks—Can be used as a clock source for the other on-chip peripherals
?On-chip RC oscillator range of 31.25 to 39.0625 kHz oscillator as the reference of FLL input.
4.5.3Memories and memory interfaces
4.5.3.1
On-chip memory
?48 MHz performance devices
?Up to 128 KB flash memory?Up to 16 KB SRAM
?Security circuitry to prevent unauthorized access to RAM and flash contents
4.5.4Analog
4.5.4.1
Analog-to-Digital Converter (ADC)
The features of the ADC module are given below.
?Linear successive approximation algorithm with 8-, 10-, or 12-bit resolution
?Up to 16 external analog inputs, and 5 internal analog inputs including internal bandgap, temperature sensor, andreferences
?Output formatted in 8-, 10-, or 12-bit right-justified unsigned format
?Single or continuous conversion (automatic return to idle after single conversion)?Supports up to eight result FIFO with selectable FIFO depth?Configurable sample time and conversion speed/power?Conversion complete flag and interrupt
?Input clock selectable from up to four sources
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PreliminaryFreescale Semiconductor, Inc.
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