SKEA128PB

Freescale SemiconductorProduct Brief

Document Number:SKEA128PBRev 1.1, 02/2014

Supports all SKEA128 devices

Product Brief

Contents

1Kinetis EA series

Kinetis EA series provide the highly scalable portfolio ofARM? Cortex?-M0+ MCUs in the automotive industry. With2.7–5.5 V supply and focus on exceptional EMC/ESD

robustness, Kinetis EA series devices are well suited to a widerange of applications in electrical harsh environments, and isoptimized for cost-sensitive applications offering low pin-count option. The Kinetis EA series offers a broad range ofmemory, peripherals, and package options. They sharecommon peripherals and pin counts allowing developers tomigrate easily within an MCU family or among the MCUfamilies to take advantage of more memory or feature

integration. This scalability allows developers to standardizeon the Kinetis EA series for their end product platforms,maximising hardware and software reuse and reducing time-to-market.

Following are the general features of the Kinetis EA seriesMCUs.

?32-bit ARM Cortex-M0+ core

?Scalable memory footprints from 8 KB flash / 1 KBSRAM to 128 KB flash / 16 KB SRAM

?Precision mixed-signal capability with on chip analogcomparator and 12-bit ADC

?Powerful timers for a broad range of applicationsincluding motor control

?Serial communication interfaces such as UART, SPI,I2C, and others.

? 2014 Freescale Semiconductor, Inc.

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Kinetis EA series.......................................................1KEA128 sub-family introduction.............................2Block diagram...........................................................3Features.....................................................................4

KEA128 sub-family introduction?High security and safety with internal watchdog and programmable CRC module

?Single power supply (2.7–5.5 V) with full functional flash program/erase/read operations?Ambient operation temperature range: –40 °C ~ 125 °C

Kinetis EA series MCU families are supported by a market-leading enablement bundle from Freescale and numerous ARMthird-party ecosystem partners. The KEA128 can be running at 48 MHz and is pin-compatible within EA series and with theFreescale's 8-bit S08RN family.

2KEA128 sub-family introduction

This sub-family includes a powerful array of analog, communication, and timing and control peripherals with specific flashmemory size and the pin count.?Core and architecture:

?ARM Cortex-M0+ core running up to 48 MHz at 125 °C with zero wait state execution from memories

?Single-cycle access to I/O: Up to 50 percent faster than standard I/O, improves reaction time to externalevents allowing bit manipulation and software protocol emulation

?Two-stage pipeline: Reduced number of cycles per instruction (CPI), enabling faster branch instruction andISR entry, and reducing power consumption

?Excellent code density in comparison to 8-bit and 16-bit MCUs: Reduced flash size, system cost, andpower consumption

?Optimized access to program memory: Accesses on alternate cycles reduces power consumption?100 percent compatible with ARM Cortex-M0 and a subset ARM Cortex-M3/M4: Reuse existingcompilers and debug tools

?Simplified architecture: 56 instructions and 17 registers enable easy programming and efficient packagingof 8/16/32-bit data in memory

?Linear 4 GB address space removes the need for paging/banking, reducing software complexity?ARM third-party ecosystem support: Software and tools to help minimize development time/cost?Bus clock running up to 24 MHz

?Bit-band: Enhanced SRAM bit operation by aliased SRAM bit-band region with Cortex-M0+ core

?BME: Bit manipulation engine reduces code size and cycles for bit-oriented operations to peripheral registers andSRAM memory eliminating traditional methods where the core would need to perform read-modify-writeoperations.

?Power-saving:

?Low-power ARM Cortex-M0+ core with excellent energy efficiency?Supports three power modes: Run, Wait and Stop

?Supports clock gating for unused modules, and specific peripherals remain working in Stop mode?Memory:

?Up to 128 KB program flash, 16 KB SRAM

?Embedded 32 B flash cache for optimizing bus bandwidth and flash execution performance?Support bit operation on SRAM domain through aliased bit-band region or BME?Clocks

?Oscillator (OSC) - supports 32.768 kHz crystal or 4 MHz to 24 MHz crystal or ceramic resonator; choice of lowpower or high gain oscillators

?Internal clock source (ICS) - internal FLL with internal or external reference, 37.5 kHz pretrimmed internalreference for 48 MHz system clock

?Internal 1 kHz low-power oscillator (LPO)?Mixed-signal analog:

?Up to 16 channels of 12-bit analog-to-digital conversion (ADC) with 2.5 μs conversion time, 1.7 mV/°Ctemperature sensor, internal bandgap reference channel, supporting automatic compare, optional hardwaretrigger, and operating in Stop mode

?Up to two analog comparators (ACMP) with both positive and negative inputs, separately selectable interrupt onrising and falling comparator output

?Human-machine interface (HMI):

?Up to two 32-bit keyboard interrupt modules (KBI)

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PreliminaryFreescale Semiconductor, Inc.

Block diagram?Connectivity and communications:

?Up to three serial communications interface (UART) modules with optional 13-bit break, full duplex non-returnto zero (NRZ) and LIN extension support

?Up to two serial peripheral interface (SPI) modules with full-duplex or single-wire bidirectional and master orslave mode

?Up to two Inter-integrated circuit ( I2C) modules with support of system management bus and I2C0 supports 4-wire interface feature

?One Freescale's scalable controller area network (MSCAN) conforming to CAN2.0A/B specification?Reliability, safety and security:

?Internal watchdog with independent clock source

?Cyclic redundancy check (CRC) with programmable 16- or 32-bit polynomial generator?Timing and control:

?FlexTimer module (FTM) including one 6-channel FTM with deadtime insertion and fault detection, and up totwo 2-channel FTMs backward compatible with TPM modules. Each channel can be configured for inputcapture, output compare, edge- or center-aligned PWM mode.

?Periodic interrupt timer (PIT) for RTOS task scheduler time base or trigger source for ADC conversion and timermodules

?16-bit pulse width timer (PWT) for positive, negative and period capture with selectable driving clock?FTM and PWT modules support separate timer clock from core and bus, up to 48 MHz?16-bit real timer counter (RTC)?I/O and package:

?Up to 71 GPIO pins with interrupt functionality?Up to 2 true open-drain output pins

?Up to 8 high current drive pins supporting 20 mA source/sink current?Multiple package options from 64-pin to 80-pinThe family acts as a low-power, high-robustness, and cost-effective microcontroller to provide developers an appropriateentry-level 32-bit solution. The family is next generation MCU solution with enhanced EMC/ESD performance for cost-sensitive, high-reliability devices applications used in high electrical noise environments.

3Block diagram

The following figure shows a superset block diagram of the device. Other devices within the family have a subset of thefeatures.

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FeaturesKinetis KEA128 Family

??ARM Cortex -M0+CoreSystemWatchdogMemories and Memory InterfacesFlashClocksFrequency-locked loopInternaloscillatorSerial wiredebug interfacesNVICBMERAM InternalreferenceclocksSecurityand IntegrityCRCx1Analog12-bit ADCx1TimersFTMs2x2ch 1x6chCommunication Human-MachineInterface (HMI)InterfacesICx2UARTx3SPIx2MSCANx12GPIOsACMPx2PITx1KBIx2RTCx1PWTx1Figure 1. KEA128 family block diagram4Features

4.1Feature summary

All devices within the KEA128 sub-family have a minimum of the following features.

Table 1.Common features among all KEA128 devicesOperating characteristics?2.7 V to 5.5 V?Temperature range (TA) -40 °C to 125 °C?Three operation modes: Run, Wait, Stop?Next generation 32-bit ARM Cortex M0+ coreTable continues on the next page...Core featuresProduct Brief, Rev 1.1, 02/2014

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PreliminaryFreescale Semiconductor, Inc.

FeaturesTable 1.Common features among all KEA128 devices (continued)?Supports up to 32 interrupt request sources?Nested vectored interrupt controller (NVIC)?2-pin serial wire debug (SWD) interfaceSystem and power management?Watchdog?Integrated bit manipulation engine (BME)?Power management controller with three differentpower modes?Non-maskable interrupt (NMI)?80-bit unique identification (ID) number?External crystal oscillator or resonator?Up to DC-48 MHz external square wave input clock?Internal clock references?31.25–39.063 kHz oscillator?1 kHz oscillator?Frequency-locked loop with the range of?40–50 MHz?Up to 128 KB flash memory?Up to 16 KB SRAM?Watchdog (WDOG)?Cyclic redundancy check (CRC) module?One 12-bit analog-to-digital converter (ADC)?Two analog comparators (ACMP) with internal 6-bitdigital-to-analog converter (DAC)?????One 6-channel and two 2-channel 16-bit FTM modules32-bit programmable interrupt timer (PIT)Pulse width timer (PWT)Real-time clock (RTC)System tick timer (SYSTICK)ClocksMemory and memory interfacesSecurity and integrityAnalogTimersCommunications?Two serial peripheral interfaces (SPI)?Two inter-integrated circuit (I2C) modules?Three universal asynchronous receiver/transmitter(UART) modules?One Freescale's scalable controller area network(MSCAN) module?Up to 71 GPIO pins?Up to two 32-bit keyboard interface (KBI) modules?Interrupt (IRQ)Human-machine interface4.2Memory and package options

The following table summarizes the memory and package options for the KEA128 family. All devices which share acommon package are pin-for-pin compatible.

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