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END A;
8.6 选择器
（1） 3选1数据选择器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY MUX3 IS PORT(
ALUOUT,RsOUT,IR_AOUT:IN STD_LOGIC_VECTOR(7 DOWNTO 0); ALU_B,Rs_B,ADDR_B:IN STD_LOGIC;
DBUS:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );
END MUX3;
ARCHITECTURE A OF MUX3 IS BEGIN
PROCESS(ALU_B,Rs_B,ADDR_B) BEGIN IF(ALU_B='0') THEN DBUS <= ALUOUT; ELSIF(Rs_B='0') THEN DBUS <= RsOUT; ELSIF(ADDR_B='0') THEN DBUS <=IR_AOUT; ELSE DBUS <= \ END IF; END PROCESS; END A;
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（2）四选一数据选择器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY MUX4_1 IS PORT(
R0,R1,R2,R3:IN STD_LOGIC_VECTOR(7 DOWNTO 0); X:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); I11,I10:IN STD_LOGIC );
END MUX4_1;
ARCHITECTURE A OF MUX4_1 IS BEGIN
PROCESS BEGIN
IF(I11='0' AND I10='0') THEN X<=R0;
ELSIF(I11='0' AND I10='1')THEN X<=R1;
ELSIF(I11='1' AND I10='0')THEN X<=R2; ELSE
X<=R3; END IF;
END PROCESS; END A;
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（3）2-4选择器
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY DECODER IS PORT(
I9,I8:IN STD_LOGIC;
Y0,Y1,Y2,Y3:OUT STD_LOGIC );
END DECODER;
ARCHITECTURE A OF DECODER IS BEGIN
PROCESS BEGIN
IF(I9='0' AND I8='0') THEN Y0<='1'; Y1<='0'; Y2<='0'; Y3<='0';
ELSIF(I9='0' AND I8='1') THEN Y0<='0'; Y1<='1'; Y2<='0'; Y3<='0';
ELSIF(I9='1' AND I8='0') THEN Y0<='0'; Y1<='0'; Y2<='1'; Y3<='0'; ELSE
Y0<='0'; Y1<='0';
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Y2<='0'; Y3<='1'; END IF; END PROCESS; END A;
8.7程序计数器
程序：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY PC IS PORT(
LOAD,LDPC,CLR: IN STD_LOGIC;
D:IN STD_LOGIC_VECTOR(7 DOWNTO 0); O: OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END PC;
ARCHITECTURE A OF PC IS
SIGNAL QOUT: STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN
PROCESS(LDPC,CLR,LOAD) BEGIN IF(CLR='0')THEN QOUT<=\ ELSIF(LDPC'EVENT AND LDPC='1')THEN IF(LOAD='0')THEN QOUT<=D; ELSE QOUT<=QOUT+1; END IF; END IF;
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END PROCESS; O<=QOUT; END A;
8.8 指令寄存器
程序： LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY IR IS PORT(
D: IN STD_LOGIC_VECTOR(15 DOWNTO 0); CLK: IN STD_LOGIC;
Q: OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END IR;
ARCHITECTURE A OF IR IS BEGIN
PROCESS(CLK) BEGIN
IF(CLK'EVENT AND CLK='1') THEN Q<=D; END IF; END PROCESS; END A;
8.9 时序产生器
程序：
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COUNTER IS PORT(
CLK,CLR: IN STD_LOGIC;
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T2,T3,T4: OUT STD_LOGIC );
END COUNTER;
ARCHITECTURE A OF COUNTER IS
SIGNAL X:STD_LOGIC_VECTOR(1 DOWNTO 0):=\BEGIN
PROCESS(CLK,CLR) BEGIN
IF(CLR='0') THEN T2<='0'; T3<='0'; T4<='0'; X<=\
ELSIF(CLK'EVENT AND CLK='1') THEN X<=X+1;
T2<=(NOT X(1))AND X(0); T3<=X(1) AND(NOT X(0)); T4<=X(1) AND X(0); END IF; END PROCESS; END A;
8.10与门
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