计算机组成原理课设论文(6)

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（4）控制存储器

程序：

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY COUNTROM IS PORT(

ADDR: IN STD_LOGIC_VECTOR(5 DOWNTO 0); UA:OUT STD_LOGIC_VECTOR(5 DOWNTO 0); D:OUT STD_LOGIC_VECTOR(19 DOWNTO 0) );

END COUNTROM;

ARCHITECTURE A OF COUNTROM IS

SIGNAL DATAOUT: STD_LOGIC_VECTOR(25 DOWNTO 0); BEGIN

PROCESS BEGIN

CASE ADDR IS WHEN \=> DATAOUT<=\ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \ WHEN \=> DATAOUT<=\ WHEN \ WHEN \=> DATAOUT<=\ WHEN OTHERS => DATAOUT<=\ END CASE;

UA(5 DOWNTO 0)<=DATAOUT(5 DOWNTO 0);

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D(19 DOWNTO 0)<=DATAOUT(25 DOWNTO 6); END PROCESS; END A;

（5）微命令寄存器

程序：

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL;

USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY MCOMMAND IS PORT(

T2,T3,T4:IN STD_LOGIC;

D:IN STD_LOGIC_VECTOR(19 DOWNTO 0);

LOAD,LDPC,LDAR,LDIR,LDRI,LDPSW,RS_B,S2,S1,S0:OUT STD_LOGIC; ALU_B,SW_B,LED_B,RD_D,CS_D,RAM_B,CS_I,ADDR_B,P1,P2:OUT STD_LOGIC );

END MCOMMAND;

ARCHITECTURE A OF MCOMMAND IS

SIGNAL DATAOUT:STD_LOGIC_VECTOR(19 DOWNTO 0); BEGIN

PROCESS(T2) BEGIN

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IF(T2'EVENT AND T2='1') THEN

DATAOUT(19 DOWNTO 0)<=D(19 DOWNTO 0); END IF;

LOAD<=DATAOUT(19);

LDPC<=DATAOUT(18) AND T4; LDAR<=DATAOUT(17) AND T3; LDIR<=DATAOUT(16) AND T3; LDRI<=DATAOUT(15) AND T4; LDPSW<=DATAOUT(14) AND T4; RS_B<=DATAOUT(13); S2<=DATAOUT(12); S1<=DATAOUT(11); S0<=DATAOUT(10); ALU_B<=DATAOUT(9); SW_B<=DATAOUT(8); LED_B<=DATAOUT(7);

RD_D<=NOT(NOT DATAOUT(6) AND (T2 OR T3)); CS_D<=NOT(NOT DATAOUT(5) AND T3); RAM_B<=DATAOUT(4); CS_I<=DATAOUT(3); ADDR_B<=DATAOUT(2); P1<=DATAOUT(1); P2<=DATAOUT(0); END PROCESS; END A;

（6）微地址转换器F2

程序：

LIBRARY IEEE; LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY F2 IS PORT(

D:IN STD_LOGIC_VECTOR(5 DOWNTO 0);

UA5,UA4,UA3,UA2,UA1,UA0: OUT STD_LOGIC ); END F2;

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ARCHITECTURE A OF F2 IS BEGIN

UA5<=D(5); UA4<=D(4); UA3<=D(3); UA2<=D(2); UA1<=D(1); UA0<=D(0); END A;

（7）指令代码转换器F3

程序：

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY F3 IS PORT(

D:IN STD_LOGIC_VECTOR(3 DOWNTO 0); UA3,UA2,UA1,UA0: OUT STD_LOGIC ); END F3;

ARCHITECTURE A OF F3 IS BEGIN

UA3<=D(3); UA2<=D(2); UA1<=D(1); UA0<=D(0); END A;

8.5寄存器单元

程序：

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

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ENTITY LS273 IS PORT(

D:IN STD_LOGIC_VECTOR(7 DOWNTO 0); O: OUT STD_LOGIC_VECTOR(7 DOWNTO 0); CLK: IN STD_LOGIC );

END LS273;

ARCHITECTURE A OF LS273 IS BEGIN

PROCESS(CLK) BEGIN IF(CLK'EVENT AND CLK='1')THEN O<=D; END IF; END PROCESS; END A;

8.6 1:2分配器

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY FEN2 IS PORT(

LED_B:IN STD_LOGIC;

DBUS:IN STD_LOGIC_VECTOR(7 DOWNTO 0);

FENOUT,OUTBUS:OUT STD_LOGIC_VECTOR(7 DOWNTO 0) );

END FEN2;

ARCHITECTURE A OF FEN2 IS BEGIN

PROCESS BEGIN

IF(LED_B='0') THEN OUTBUS<=DBUS; ELSE

FENOUT<=DBUS; END IF;

END PROCESS;

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