EM78P372N数据手册(21)

EM78P372N数据手册

EM78P372N8-Bit Microcontroller6.1.12 Bank 0 RD (ADDATA1L: Converted Value of ADC)Bit 7 AD7 Bit 6 AD6 Bit 5 AD5 Bit 4 AD4 Bit 3 AD3 Bit 2 AD2 Bit 1 AD1 Bit 0 AD0When AD conversion is completed, the result is loaded into the ADDATA1L. The ADRUN bit is cleared and the ADIF is set. See Section 6.1.13, RE (Interrupt Status 2 and Wake-up Control Register). RD is read only6.1.13 Bank 0 RE (Interrupt Status 2 and Wake-up Control Register)Bit 7 /LVD Bit 6 LVDIF Bit 5 ADIF Bit 4 CMPIF Bit 3 ADWE Bit 2 CMPWE Bit 1 ICWE Bit 0 LVDWENote: 1. RE <6, 5, and 4> can be cleared by instruction but cannot be set. 2. IOCE0 is the interrupt mask register. 3. Reading RE will result to “Logic AND” of the RE and IOCE0.Bit 7 (/LVD): Low voltage Detector state. This is a read only bit. When the VDD pin voltage is lower than LVD voltage interrupt level (selected by LVD1 and LVD0), this bit will be cleared. 0: Low voltage is detected 1: Low voltage is not detected or LVD function is disabled (default) Bit 6 (LVDIF): Low Voltage Detector Interrupt flag LVDIF is reset to “0” by software. Bit 5 (ADIF): Interrupt flag for analog to digital conversion. Set when AD conversion is completed. Reset by software. 0: no interrupt occurs (default) 1: interrupt request Bit 4 (CMPIF): Comparator Interrupt flag. Set when a change occurs in the Comparator output. Reset by software. 0: no interrupt occurs (default) 1: interrupt request Bit 3 (ADWE): ADC wake-up enable bit 0: Disable ADC wake-up (default) 1: Enable ADC wake-up When AD Conversion enters sleep/idle mode, this bit must be set to “Enable“.Product Specification (V1.1) 05.24.2011(This specification is subject to change without further notice) 15

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