EM78P372N数据手册(18)

EM78P372N数据手册

EM78P372N8-Bit Microcontroller6.1.8 Bank 0 R9 (ADCON: ADC Control Register)Bit 7 VREFS Bit 6 CKR1 Bit 5 CKR0 Bit 4 ADRUN Bit 3 ADPD Bit 2 ADIS2 Bit 1 ADIS1 Bit 0 ADIS0Bit 7 (VREFS): The input source of Vref of the ADC 0: The Vref of the ADC is connected to Vdd (default value), and the VREF/TCC/P54 pin carries out the function of P54 (default) 1: The Vref of the ADC is connected to VREF/TCC/P54NOTE The P54/TCC/VREF pin cannot be applied to TCC and VREF at the same time. If P54/TCC/VREF functions as VREF analog input pin, then CONT Bit 5 “TS” must be “0.” The VREF/TCC/P54 Pin Priority is as follows: P53/TCC/VREF Pin Priority High VREF Medium TCC Low P54Bit 6 and Bit 5 (CKR1 and CKR0): The prescaler of ADC oscillator clock rate 00 = 1 : 16 (default value) 01 = 1 : 4 10 = 1 : 64 11 = 1 : 1Max. Operation Frequency ( if TAD=4μs, match 372N ) 4 MHz 1 MHz 16 MHz 16K/128kHz Max. Operation Frequency ( if TAD=1μs, match 372N ) 16 MHz 4 MHz 1 MHz 16K/128kHzCPUSCKR1 : CKR0Operation Mode1 1 1 1 000 (default) 01 10 11 ××FOSC/16 FOSC/4 FOSC/64 FOSC/1 Bit 4 (ADRUN): ADC starts to RUN. 0: Reset upon completion of the conversion. This bit cannot be reset through software (default) 1: an AD conversion is started. This bit can be set by software Bit 3 (ADPD): ADC Power-down mode 0: Switch off the resistor reference to save power even while the CPU is operating (default) 1: ADC is operating12 Product Specification (V1.1) 05.24.2011(This specification is subject to change without further notice)

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