基于FPGA实现的1553B编解码Verilog源代码(2)

else if (sync_csw || sync_dw) cnt_enb <= 1'b1 ; else if (cnt == 'd131) cnt_enb <= 1'b0 ; else

cnt_enb <= cnt_enb ; end

always @(posedge dec_clk or negedge rst_n) begin if (!rst_n ) cnt <= 8'hFF ; else if (cnt_enb) cnt <= cnt + 1 ; else if (!cnt_enb) cnt <= 8'hFF ; else

cnt <= cnt ; end

// Generate data sample points.

assign data_sample = (~cnt[2] & ~cnt[1] & ~cnt[0]) ;

// register data at every sample point through shift register. always @(posedge dec_clk or negedge rst_n) begin if (!rst_n )

dword_int <= 17'h0000 ;

else if (data_sample && cnt_enb)

dword_int <= {dword_int[1:16],~data_sftreg[2]} ; else if (!cnt_enb)

dword_int <= 17'h0000 ; else

dword_int <= dword_int ; end

// Register command and status sync patter type till the end // of data word.

always @(posedge dec_clk or negedge rst_n) begin if (!rst_n )

sync_csw_reg <= 1'b0 ; else if (sync_csw)

sync_csw_reg <= 1'b1 ; else if (cnt == 'd132)

sync_csw_reg <= 1'b0 ; else

sync_csw_reg <= sync_csw_reg ; end

// Register data sync patter type till the end of data word. always @(posedge dec_clk or negedge rst_n) begin if (!rst_n )

sync_dw_reg <= 1'b0 ; else if (sync_dw)

sync_dw_reg <= 1'b1 ; else if (cnt == 'd132)

sync_dw_reg <= 1'b0 ; else

sync_dw_reg <= sync_dw_reg ; end

// Register the parallel data word and control outputs. always @(posedge dec_clk or negedge rst_n) begin if (!rst_n ) begin

rx_dword <= 16'h0000 ; rx_dval <= 1'b0 ; rx_perr <= 1'b0 ; rx_csw <= 1'b0 ; rx_dw <= 1'b0 ; end

else if (cnt == 'd131) begin

rx_dword <= dword_int[0:15] ; rx_dval <= 1'b1 ;

rx_perr <= ((^dword_int[0:15]) != dword_int[16]) ; rx_csw <= sync_csw_reg ; rx_dw <= sync_dw_reg ; end

else begin

rx_dword <= 16'h0000 ; rx_dval <= 1'b0 ; rx_perr <= 1'b0 ; rx_csw <= 1'b0 ; rx_dw <= 1'b0 ; end end

endmodule

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