五、阅读程序，将实体部分补充完整，并画出输出信号y的时序图 （20分） 1、a和b的取值范围为0-15 LIBRARY ieee;
USE ieee.std_logic_1164.all; entity v13 is
end v13;
architecture example OF v13 is begin
process(a,b) begin
if(a=b) then q<=\ elsif(a>b) then q<=\ else
q<=\ end if; end process; end example;
port(a,b: in std_logic_vector(3 downto 0); q: out std_logic_vector(2 downto 0));
2、
LIBRARY ieee;
USE ieee.std_logic_1164.ALL; ENTITY bcd7 IS
END bcd7;
ARCHITECTURE abc OF bcd7 IS
SIGNAL din : STD_LOGIC_vector(3 downto 0); SIGNAL dout : STD_LOGIC_vector(6 downto 0); BEGIN
din<=d3&d2&d1&d0; process(din) begin
case din is
when \
when \ when \ when \ when \ when \ when \ when \ when \ when \ when others => dout<=\ end case; end process; a<=dout(6); b<=dout(5); c<=dout(4); d<=dout(3); e<=dout(2); f<=dout(1); g<=dout(0); END abc;
--display 1 --display 2 --display 3 --display 4 --display 5 --display 6 --display 7 --display 8 --display 9 --display E
PORT(
d3,d2,d1,d0 : IN STD_LOGIC; a,b,c,d,e,f,g : OUT STD_LOGIC);
3、1位十进制计数器的VHDL描述，试补充完整。 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT10 IS
PORT ( CLK : IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)) ; END CNT10;
ARCHITECTURE bhv OF CNT10 IS
SIGNAL Q1 : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
PROCESS (CLK) BEGIN
IF CLK'EVENT AND CLK = '1' THEN -- 边沿检测 IF Q1 > 10 THEN
Q1 <= (OTHERS => '0'); -- 置零 ELSE
Q1 <= Q1 + 1 ; -- 加1 END IF; END IF; END PROCESS ; Q <= Q1; END bhv;
4、多路选择器的VHDL描述，试补充完整。 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; ENTITY bmux IS
PORT ( sel : IN STD_LOGIC;
A, B : IN STD_LOGIC_VECTOR(7 DOWNTO 0); Y : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)) ; END bmux;
ARCHITECTURE bhv OF bmux IS BEGIN
y <= A when sel = '1' ELSE B; END bhv;
六、编程
1、请用With_Select_Then或When_Else分别编写一个4选1的数据选择器，如右图。要求：输入信号（1位）为a，b，c，d，选择信号（2位）为s，输出信号为x，当s为“00”输出a，“01”输出b，“10”输出c，其他情况输出d，使用STD_LOGIC数据类型。 LIBRARY ieee;
USE ieee.std_logic_1164.all; ENTITY mux IS
PORT ( a,b,c,d : IN STD_LOGIC;
s: IN STD_LOGIC_VECTOR(1 DOWNTO 0); x : OUT STD_LOGIC); END mux;
ARCHITECTURE example OF mux IS BEGIN
WITH s SELECT
x <= a WHEN \ b WHEN \ c WHEN \ d WHEN OTHERS; END example;
2、带计数使能的异步复位计数器
输入端口： clk 时钟信号
rst 异步复位信号 en 计数使能 load 同步装载
data （装载）数据输入，位宽为10
输出端口： q 计数输出，位宽为10 LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY CNT1024 IS
PORT ( CLK, RST, EN, LOAD : IN STD_LOGIC;
DATA : IN STD_LOGIC_VECTOR (9 DOWNTO 0); Q : OUT STD_LOGIC_VECTOR (9 DOWNTO 0) ); END CNT1024;
ARCHITECTURE ONE OF CNT1024 IS BEGIN
PROCESS (CLK, RST, EN, LOAD, DATA)
VARIABLE Q1 : STD_LOGIC_VECTOR (9 DOWNTO 0); BEGIN
IF RST = '1' THEN
Q1 := (OTHERS => '0');
ELSIF CLK = '1' AND CLK'EVENT THEN IF LOAD = '1' THEN Q1 := DATA; ELSE
IF EN = '1' THEN Q1 := Q1 + 1; END IF; END IF; END IF; Q <= Q1; END PROCESS; END ONE;
3、用VHDL语言编写完整的同步复位D触发器。要求：输入信号为cp,d,rst,输出为q，下降沿触发，rst高电平有效。 LIBRARY ieee;
use ieee.std_logic_1164.all; entity v15 is
port(cp,d,rs: in std_logic; q: out std_logic); end v15;
architecture behave of v15 is begin
process(cp) begin
if (cp'event and cp='0') then if rst='1' then q<='0'; else
q<=d; end if; end if; end process; end behave;
4、用VHDL语言编写完整的3-8译码器。输入信号用a、b、c表示，定义为std_logic，输出用y表示，定义为std_logic_vector，写出完整的程序。
LIBRARY ieee;
USE ieee.std_logic_1164.all; entity v12 is
port(a,b,c: in std_logic;
y: out std_logic_vector(7 downto 0)); end v12;
architecture example OF v12 is
signal indata: std_logic_vector(2 downto 0); begin
indata<=c&b&a; process(indata) begin
case indata is
when \ when \ when \ when \ when \ when \ when \ when \ when others=>NULL; end case; end process; end example;
四.（30分）设计：8选1数据选择器，用VHDL写出源程序。其中：D7—D0是数据输入端，S2、S1和S0是控制输入端，Y是数据输出端。当S2、S1、S0=“000”时，D0数据被选中，输出Y=D0；当S2、S1、S0=“001”时，D1数据被选中，输出Y=D1，以次类推。 程序填空题（类似）
下面程序是带异步复位、同步置数和移位使能的8位右移移位寄存器的VHDL描述，试补充完整。 library ieee;
use IEEE.STD-LOGIC-1165 .all; entity sreg8b is
port ( clk, rst : in std_logic; load,en : in std_logic;
din : in STD_LOGIC_VECTOR (7 downto 0); qb : out std_logic); end sreg8b;
architecture behav of SREG8B is
signal reg8 : std_logic_vector( 7 downto 0); begin
process (clk, RST , load, en) begin
if rst='1' then ――异步清零 reg8 <= (OTHERS=>'0') ;
elsif CLK'EVENT AND CLK='1' then ――边沿检测 if load = '1' then ――同步置数 reg8 <= din;
elsif en='1' then ――移位使能 reg8(6 downto 0) <= reg8(7 downto 1) ;
end if; __end if ____; end process;
qb <= _reg8(0)___; ――输出最低位 end behav; 序列检测答案 library ieee;
use ieee.std_logic_1164.all; entity se is
port(din,clk,clr : in std_logic; ab : out std_logic); end se;
architecture behav of se is
type fsm_st is (s0,s1,s2,s3,s4); signal cstate,nstate : fsm_st; begin
reg:process(clr,clk) begin
if clr='1' then cstate <= s0; --ab <= '0'; elsif clk = '1' and clk'event then cstate <= nstate; end if; end process;
com:process(cstate,din) begin
case cstate is
when s0 => if din = '1' then nstate <= s1; else nstate <= s0; end if; ab <= '0';
when s1 => if din = '1' then nstate <= s2; else nstate <= s0; end if; ab <= '0';
when s2 => if din = '1' then nstate <= s2; else nstate <= s3; end if; ab <= '0';
when s3 => if din = '1' then nstate <= s4; else nstate <= s0; end if; ab <= '0';
when s4 => if din = '1' then nstate <= s1; else nstate <= s0; end if; ab <= '1'; end case; end process; end behav;
百度搜索“77cn”或“免费范文网”即可找到本站免费阅读全部范文。收藏本站方便下次阅读，免费范文网，提供经典小说综合文库CPLD题库(4)在线全文阅读。
相关推荐：