基于VHDL的交通灯设计与实现(4)

mux <= '1' when init, '0' when others;

--control the initialization sequence with cur_state select init_init <= '1' when init,

'0' when others; --register select with cur_state select

LCD_RS <= '0' when function_set|entry_set|set_display|clr_display|set_addr, '1' when others; --what byte to transmit to lcd

--refer to datasheet for an explanation of these values

with cur_state select

tx_byte <= \ -- ??????? \ \ \ \ \ \ \ \ \ \ \ \ \ \ --main state machine

display: process(clk, rst_n) begin if(rst_n='0') then cur_state <= function_set; elsif(clk='1' and clk'event) then case cur_state is --refer to intialize state machine below when init => if(init_done = '1') then cur_state <= function_set; else cur_state <= init; end if; --every other state but pause uses the transmit state machine

when function_set => if(i2 = 2000) then cur_state <= entry_set; else cur_state <= function_set; end if;

when entry_set => if(i2 = 2000) then cur_state <= set_display; else cur_state <= entry_set; end if;

when set_display => if(i2 = 2000) then cur_state <= clr_display; else cur_state <= set_display; end if;

when clr_display => i3 <= 0; if(i2 = 2000) then cur_state <= pause; else cur_state <= clr_display; end if; when pause => if(i3 = 82000) then cur_state <= set_addr; i3 <= 0; else cur_state <= pause; i3 <= i3 + 1; end if;

when set_addr => if(i2 = 2000) then cur_state <= max_degree_1; else cur_state <= set_addr; end if;

when max_degree_1 => if(i2 = 2000) then cur_state <= max_degree_2; else

cur_state <= max_degree_1; end if;

when max_degree_2 => if(i2 = 2000) then cur_state <= blank1; else cur_state <= max_degree_2; end if; when blank1 => if(i2 = 2000) then cur_state <= temperature_1; else cur_state <= blank1; end if;

when temperature_1 => if(i2 = 2000) then cur_state <= temperature_2; else cur_state <= temperature_1; end if;

when temperature_2 => if(i2 = 2000) then cur_state <= blank2; else cur_state <= temperature_2; end if; when blank2 => if(i2 = 2000) then cur_state <= degree_1; else cur_state <= blank2; end if;

when degree_1 => if(i2 = 2000) then cur_state <= degree_2; else cur_state <= degree_1; end if;

when degree_2 => if(i2 = 2000) then cur_state <= blank3; else cur_state <= degree_2; end if;

when blank3 => if(i2 = 2000) then cur_state <=set_addr ; else cur_state <= blank3; end if; end case; end if; end process display; with mux select SF_D <= SF_D0 when '0', --transmit SF_D1 when others; --initialize with mux select LCD_E <= LCD_E0 when '0', --transmit LCD_E1 when others; --initialize --specified by datasheet transmit : process(clk, rst_n, tx_init) begin if(rst_n='0') then tx_state <= done; elsif(clk='1' and clk'event) then case tx_state is when high_setup => --40ns LCD_E0 <= '0'; SF_D0 <= tx_byte(7 downto 4); if(i2 = 2) then tx_state <= high_hold; i2 <= 0; else tx_state <= high_setup; i2 <= i2 + 1; end if; when high_hold => --230ns LCD_E0 <= '1'; SF_D0 <= tx_byte(7 downto 4); if(i2 = 12) then tx_state <= oneus; i2 <= 0; else tx_state <= high_hold; i2 <= i2 + 1; end if; when oneus => LCD_E0 <= '0';

if(i2 = 50) then tx_state <= low_setup; i2 <= 0; else tx_state <= oneus; i2 <= i2 + 1; end if;

when low_setup => LCD_E0 <= '0'; SF_D0 <= tx_byte(3 downto 0); if(i2 = 2) then tx_state <= low_hold; i2 <= 0; else tx_state <= low_setup; i2 <= i2 + 1; end if;

when low_hold => LCD_E0 <= '1'; SF_D0 <= tx_byte(3 downto 0); if(i2 = 12) then tx_state <= fortyus; i2 <= 0; else tx_state <= low_hold; i2 <= i2 + 1; end if;

when fortyus => LCD_E0 <= '0'; if(i2 = 2000) then tx_state <= done; i2 <= 0; else tx_state <= fortyus; i2 <= i2 + 1; end if; when done => LCD_E0 <= '0'; if(tx_init = '1') then tx_state <= high_setup; i2 <= 0; else tx_state <= done; i2 <= 0;

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