基于VHDL的交通灯设计与实现(3)

波形仿真

分别给主干道，支干道个颜色灯持续时间赋值，再给定，当前亮灯的剩余时间，然后又进行仿真，结果符合预期

? LED模块代码

波形仿真

分别给予输入不同周期的高低点评，相互叠加的结果符合预期。

? LCD模块代码

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity LCD is port( clk : in STD_LOGIC; rst_n : in STD_LOGIC; counter_play1h, counter_play1l : in STD_LOGIC_VECTOR(3 downto 0); counter_play2h, counter_play2l : in STD_LOGIC_VECTOR(3 downto 0);

--degree1, degree2 : in STD_LOGIC_VECTOR(3 downto 0); SF_D : out STD_LOGIC_VECTOR(3 downto 0); LCD_E, LCD_RS, LCD_RW: out STD_LOGIC ); end LCD;

architecture behavior of LCD is type tx_sequence is (high_setup, high_hold, oneus, low_setup, low_hold, fortyus, done);

signal tx_state : tx_sequence := done; signal tx_byte : std_logic_vector(7 downto 0); signal tx_init : std_logic := '0'; type init_sequence is (idle, fifteenms, one, two, three, four, five, six, seven, eight, done);

signal init_state : init_sequence := idle; signal init_init, init_done : std_logic := '0'; signal i : integer range 0 to 750000 := 0; signal i2 : integer range 0 to 2000 := 0; signal i3 : integer range 0 to 82000 := 0; signal SF_D0, SF_D1 : std_logic_vector(3 downto 0); signal LCD_E0, LCD_E1 : std_logic; signal mux : std_logic;--???? type display_state is (init, function_set, entry_set, set_display, clr_display, pause, set_addr,

max_degree_1,max_degree_2,temperature_1,temperature_2,degree_1,degree_2,blank1,blank2,blank3);

signal cur_state : display_state := init; begin --LED <= tx_byte; --for diagnostic purposes --SF_CE0 <= '1'; --disable intel strataflash LCD_RW <= '0'; --write only --The following \ --when to transmit a command/data and when not to with cur_state select tx_init <= '0' when init | pause , '1' when others; --control the bus with cur_state select

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