3. 二路选择器的设计： VHDL语言描述：
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all;
entity dex2 is
port(panduan,wubai,yiqian:instd_logic; shuchu:outstd_logic); end entity dex2;
architecture behave of dex2 is begin
process(panduan,wubai,yiqian) begin
if(panduan='0') then shuchu<=wubai;
//当panduan为0时，输出wubai端口的输入
else shuchu<=yiqian;//否则shuchu端口输出yiqian的端口输入 end if; end process; end behave;
4. 分频器的设计： VHDL语言描述：
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity fenpin is
port(clk:instd_logic;
hz1,hz4,hz64,hz512:out std_logic); end entity fenpin;
architecture behavior of fenpin is
signal q:std_logic_vector(9 downto 0); begin process(clk) begin
if(rising_edge(clk)) then q<=q+1;
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end if;
end process; hz1<=q(9); hz4<=q(7); hz64<=q(3); hz512<=q(0);
end behavior;//将1KHz分为1Hz、4Hz、64Hz、512Hz输出
5. 动态扫描的设计： VHDL语言描述：
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;
entity dtsm is
port( clk:instd_logic;
s:in std_logic_vector(7 downto 0); m:in std_logic_vector(7 downto 0); h:in std_logic_vector(7 downto 0); ledag:outstd_logic_vector(6 downto 0); sel:outstd_logic_vector(2 downto 0)); end dtsm;
architecture behave of dtsm is
signal out1:std_logic_vector(3 downto 0);
signal sel1:std_logic_vector(2 downto 0); begin
p1:process(clk) begin
if rising_edge(clk) then //当有一个上升沿脉冲 sel1<=sel1+1;//sel自增1 end if; sel<=sel1;
end process p1;
p2:process(sel1,s,h,m)
begin
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case sel1 is
when \//扫描数码管的第二位，即h的十位 when \//扫描数码管的第一位，即h的十位 when \//扫描数码管第四位，即m的个位 when \ //扫描数码管第三位，即m的十位 when \ //扫描数码管第七位，即s的个位 when \//扫描数码管第六位，即s的十位 when others=>out1<=\ end case;
end process p2;
p3:process(out1)
begin
case out1 is
when \ when \ when \ when \ when \ when \ when \ when \ when \ when \ when \；
//将0~9翻译显示在七段数码管上
when others=>ledag<=\；
//当不是0~9时，不显示
end case;
end process p3; end behave;
6. 整点报时功能的设计： VHDL语言描述：
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;
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entity zdbs is
port( s:in std_logic_vector(7 downto 0); m:in std_logic_vector(7 downto 0); shuchu,panduan:outstd_logic); end entity zdbs;
architecture behave of zdbs is begin
p1:process(s,m) begin
if(((\downto 0))and(\downto 4))and(\downto 4))and s(3 downto 0)=\
((\downto 0))and(\downto 4))and(\downto 4))and s(3 downto 0)=\
((\downto 0))and(\downto 4))and(\downto 4))and s(3 downto 0)=\
((\downto 0))and(\downto 4))and(\downto 4))and s(3 downto 0)=\
((\downto 0))and(\downto 4))and(\downto 4))and s(3 downto 0)=\
//当分钟为59分，且秒钟为50秒、52秒、54秒、56秒、58秒时， panduan输出1，shuchu输出0（即低音报时）
elsif((\downto 0))and(\downto 4))and(\downto 4))and s(3 downto 0)=\//当分钟和秒钟都为0，即整点时，panduan输出1， shuchu输出1（即高音报时）
else panduan<='0';//否则panduan输出0，即不报时 end if;
end process; end behave;
7. 选择显示与闹钟设置的设计： VHDL语言描述：
library ieee;
use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all;
entity nz is
port( shuru:instd_logic;
ndm:instd_logic_vector(7 downto 0); ndh:instd_logic_vector(7 downto 0);
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m:in std_logic_vector(7 downto 0); h:in std_logic_vector(7 downto 0); outh:outstd_logic_vector(7 downto 0); outm:outstd_logic_vector(7 downto 0); shuchu:outstd_logic); end nz;
architecture behave of nz is begin
process(shuru,ndm,ndh,m,h) begin
if(shuru='0')then outm(7 downto 0)<=m(7 downto 0);outh(7 downto 0)<=h(7 downto 0);
//如果shuru等于0，则输出显示现在时间
if(ndm(7 downto 0)=m(7 downto 0)and ndh(7 downto 0)=h(7 downto 0))then shuchu<='1';
//如果现在时间和设定的闹钟时间相等，则shuchu输出1(闹钟响) else shuchu<='0'; //否则shuchu输出0（闹钟不响） end if;
else outm(7 downto 0)<=ndm(7 downto 0);outh(7 downto 0)<=ndh(7 downto0);shuchu<='0';
//如果shuru等于1，则输出显示闹钟的时间 end if; end process; end behave;
四、顶层图
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