FPGA复习题(5)

if(flag==4'h8) begin flag<=4'h0; control_out<=1'b0; end

else flag<=flag+1'b1; end else begin

state_bing_in<=bing_in; control_out<=1'b0; end end endmodule

/////串并转换

module chuanbing_in(clock,reset_n,chuan_in,bing_out,control_in); input clock,reset_n,chuan_in,control_in; output[7:0] bing_out;

reg [7:0] bing_out;

always @ (negedge clock or negedge reset_n) begin if(!reset_n) begin bing_out<=8'hxx; end

else if(control_in==1'b1) begin

bing_out<={bing_out[6:0],chuan_in}; end

else bing_out<=8'hxx; end endmodule

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