FPGA复习题(4)

end

end

////////生成读地址

assign rd_addr_bijiao=rd_addr; always @ (clock_out or reset_n) begin

if(!reset_n) begin rd_addr<=4'h8; end

else if(rd_en) begin

rd_addr<=rd_addr+1'b1; end

end

////////////////用D触发器打两下读地址，和写地址比较看是否写满

D_D

rd(.clock(clock_out),.reset_n(reset_n),.data_in(wr_addr_bijiao),.data_out(wr_addr_w));

always @ (posedge clock_out or negedge reset_n)

begin

if(!reset_n) begin E_flag<=1'b0; end

else if(rd_addr_bijiao==wr_addr_w) begin E_flag<=1'b1; end

else begin E_flag<=1'b0; end

end

////////////用D触发器打两下写地址，和读地址比较看是否读空 D_D

wr(.clock(clock_in),.reset_n(reset_n),.data_in(rd_addr_bijiao),.data_out(rd_addr_w));

always @ (posedge clock_in or negedge reset_n)

begin

if(!reset_n) begin F_flag<=1'b0;

end

else if(wr_addr_bijiao==rd_addr_w) begin F_flag<=1'b1; end

else begin F_flag<=1'b0; end

end

RAM16X8

ZD(.wr_clk(clock_in),.wr_en(wr_en),.wr_addr(wr_addr_bijiao),.data_in(data_in),

.rd_clk(clock_out),.rd_en(rd_en),.rd_addr(rd_addr_bijiao),.data_out(data_out));

endmodule

4.各种计数器的设计（包括分频器的设计），如作业题。 5.移位寄存器的设计，设计一个8位的移位寄存器。

6.串并、并串转换器的设计，分别完成8位的串并和并串转换电路。

////两个模块综合完成从并转串，再从串转并

module chuanbing(clock,reset_n,bing_in,bing_out,control); input clock,reset_n,control; input [7:0] bing_in;

output [7:0] bing_out;

wire [7:0] bing_out; wire control_inout; wire chuan_inout;

chuanbing_in

shou(.clock(clock),.reset_n(reset_n),.chuan_in(chuan_inout),.bing_out(bing_out),.control_in(control_inout));

chuanbing_out

fa(.clock(clock),.reset_n(reset_n),.bing_in(bing_in),.chuan_out(chuan_inout),.control_in(control),.control_out(control_inout)); endmodule

////并串转换 module

chuanbing_out(clock,reset_n,bing_in,chuan_out,control_in,control_out); input clock,reset_n,control_in; input [7:0] bing_in;

output chuan_out,control_out; reg control_out,chuan_out;

reg [7:0] state_bing_in;//chang_bing_in; reg [3:0] flag;

always @ (posedge clock or negedge reset_n ) begin if(!reset_n) begin

state_bing_in<=8'bxxxx_xxxx; control_out<=1'b0; flag<=4'h0; end

else if(control_in==1'b1) begin

chuan_out<=state_bing_in[7]; state_bing_in<=state_bing_in<<1; control_out<=1'b1;

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