MT7621_Datasheet_v0_3(19)

MT7621 Network Processor

2.3.7.1 Pin share function description Pin Share Name I/O PCMDTX PCMDRX PCMCLK O I I/O

Pin Share Function description

PCM Data Transmit DATA signal sent from the PCM host to the external codec. PCM Data Receive DATA signal sent from the external codec to the PCM host.

PCMFS

I/O

PCM SYNC signal. In our design, the direction of this signal is independent of the direction of PCMCLK. Its direction and mode is configurable. I S Data output2 2

I2SSDO I2SWS

O I/O

I S Channel Selection (or Word selection) In master mode the pin data direction is set to output, in slave mode it is set to input. I S clock In master mode the pin data direction is set to output, in slave mode it is set to input. SDXC write protect SDXC clock SDXC card detection SDXC command/ Bus state SDXC DATA line bit 0 SDXC DATA line bit 1 SDXC DATA line bit 2 SDXC DATA line bit 3 SPI chip select 0 SPI chip select 1 SPI clock Master input/Slave output Master output/Slave input GPO function GPO function SPDIF transmit

SD_WP SD_CLK SD_CD SD_CMD SD_DATA0 SD_DATA1 SD_DATA2 SD_DATA3 SPI_CS0 SPI_CS1 SPI_CLK

ED

M

SPI_MISO SPI_MOSI SPI_WP SPI_HOLD SPDIF_TX

MT7621_Data_Sheet_v0.2

IA

TE

I I

O

I/O I/O I/O I/O I/O O O O I/O I/O O O O

K

I2SCLK

I/O

2

CO

I2SSDI

I

I S Data input

2

NF

PCM Clock The clock signal can be generated by the PCM host (Output direction), or provided by an external clock (input direction). The clock frequency should match the slot configuration of the PCM host. e.g. 4 slots, PCM clock out/in should be 256 kHz. 8 slots, PCM clock out/in should be 512 kHz. 16 slots, PCM clock out/in should be 1.024 MHz. 32 slots, PCM clock out/in should be 2.048 MHz. 64 slots, PCM clock out/in should be 4.096 MHz. 128 slots, PCM clock out/in should be 8.192 MHz.

ID

EN

TI

ALPage 19 of 44

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