NAND128W3A0BZA6F中文资料(6)

While the device is busy programming or erasing,Chip Enable transitions to High, VIH, are ignoredand the device does not revert to the Standbymode.

While the device is busy reading:■the Chip Enable input should be held Low

during the whole busy time (tBLBH1) for

devices that do not present the Chip Enable Don’t Care option. Otherwise, the read

operation in progress is interrupted and the device reverts to the Standby mode. ■for devices that feature the Chip Enable Don't

Care option, Chip Enable going High during the busy time (tBLBH1) will not interrupt the read operation and the device will not revert to the Standby mode.the sequential data output during Read opera-tions. Data is valid t column address counter by one.

controls writing to the Command Interface, InputAddress and Data latches. Both addresses anddata are latched on the rising edge of Write En-able.

During power-up and power-down a recovery timeof 1µs (min) is required before the Command Inter-face is ready to accept a command. It is recom-mended to keep Write Enable high during therecovery time.

The Write Protect pin is aninput that gives a hardware protection against un-wanted program or erase operations. When WriteProtect is Low, VIL, the device does not accept anyprogram or erase operations.

It is recommended to keep the Write Protect pinLow, VIL, during power-up and power-down.is an open-drain output that can be used to identifyif the P/E/R Controller is currently active.

When Ready/Busy is Low, VOL, a read, program orerase operation is in progress. When the operationcompletes Ready/Busy goes High, VOH.

The use of an open-drain output allows the Ready/Busy pins from several memories to be connectedto a single pull-up resistor. A Low will then indicatethat one, or more, of the memories is busy.

Refer to the Ready/Busy Signal Electrical Charac-teristics section for details on how to calculate thevalue of the pull-up resistor.

VDD Supply Voltage.VDD provides the powersupply to the internal core of the memory device.It is the main power supply for all operations (read,program and erase).

An internal voltage detector disables all functionswhenever VDD is below 2.5V (for 3V devices) or1.5V (for 1.8V devices) to protect the device fromany involuntary program/erase during power-tran-sitions.

Each device in a system should have VDD decou-pled with a 0.1µF capacitor. The PCB track widthsshould be sufficient to carry the required programand erase currents

VSS Ground.Ground, VSS, is the reference forthe power supply. It must be connected to the sys-tem ground.

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元器件交易网

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

BUS OPERATIONS

There are six standard bus operations that controlthe memory. Each of these is described in thissection, see Table 5.,Bus Operations, for a sum-mary.

Command Input

Command Input bus operations are used to givecommands to the memory. Command are accept-ed when Chip Enable is Low, Command Latch En-able is High, Address Latch Enable is Low andRead Enable is High. They are latched on the ris-ing edge of the Write Enable signal.

Only I/O0 to I/O7 are used to input commands. See Figure 23. and Table 20. for details of the tim-ings requirements.Address Input

Address Input bus operations are used to input thememory address. Three bus cycles are required toinput the addresses for the 128Mb and 256Mb de-vices and four bus cycles are required to input theaddresses for the 512Mb and 1Gb devices (referto Tables 6 and 7, Address Insertion).

The addresses are accepted when Chip Enable isLow, Address Latch Enable is High, CommandLatch Enable is Low and Read Enable is High.They are latched on the rising edge of the WriteEnable signal. Only I/O0 to I/O7 are used to inputaddresses.

See Figure 24. and Table 20. for details of the tim-ings requirements.Data Input

Data Input bus operations are used to input thedata to be programmed. Table 5. Bus Operations

Bus OperationCommand InputAddress InputData InputData OutputWrite ProtectStandby

VILVILVILVILXVIH

ALVILVIHVILVILXX

CLVIHVILVILVILXX

VIHVIHVIHFallingXX

RisingRisingRisingVIHXX

X(2)XXXVILX

I/O0 - I/O7CommandAddressData InputData Output

XX

I/O8 - I/O15(1)

XXData InputData Output

XX

Data is accepted only when Chip Enable is Low,Address Latch Enable is Low, Command LatchEnable is Low and Read Enable is High. The datais latched on the rising edge of the Write Enablesignal. The data is input sequentially using theWrite Enable signal.

See Figure 25. and Table 20. and Table 21. for de-tails of the timings requirements.Data Output

Data Output bus operations are used to read: thedata in the memory array, the Status Register, theElectronic Signature and the Serial Number.

Data is output when Chip Enable is Low, Write En-able is High, Address Latch Enable is Low, andCommand Latch Enable is Low.

The data is output sequentially using the Read En-able signal.

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