NAND128W3A0BZA6F中文资料

元器件交易网

NAND128-A, NAND256-ANAND512-A, NAND01G-A

128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16)

528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories

FEATURES SUMMARY

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HIGH DENSITY NAND FLASH MEMORIES–––

Up to 1 Gbit memory arrayUp to 32 Mbit spare area

Cost effective solutions for mass storage applicationsx8 or x16 bus widthMultiplexed Address/ DataPinout compatibility for all densities1.8V device: VDD = 1.7 to 1.95V3.0V device: VDD = 2.7 to 3.6Vx8 device: (512 + 16 spare) Bytesx16 device: (256 + 8 spare) Wordsx8 device: (16K + 512 spare) Bytesx16 device: (8K + 256 spare) WordsRandom access: 12µs (max)Sequential access: 50ns (min)Page program time: 200µs (typ)

Fast page copy without external buffering

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NAND INTERFACE–––

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SUPPLY VOLTAGE––

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PAGE SIZE––

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BLOCK SIZE––

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PAGE READ / PROGRAM–––

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DATA INTEGRITY––

100,000 Program/Erase cycles10 years Data Retention

Lead-Free Components are Compliant with the RoHS Directive

Error Correction Code software and hardware models

Bad Blocks Management and Wear Leveling algorithms

File System OS Native reference softwareHardware simulation models

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COPY BACK PROGRAM MODE–

FAST BLOCK ERASE–

Block erase time: 2ms (Typ)

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RoHS COMPLIANCE–

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STATUS REGISTERELECTRONIC SIGNATURE

CHIP ENABLE ‘DON’T CARE’ OPTION–

Simple interface with microcontroller

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SERIAL NUMBER OPTIONHARDWARE DATA PROTECTION–

Program/Erase locked during Power transitions

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DEVELOPMENT TOOLS

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February 2005

元器件交易网

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

Table 1. Product List

Reference

Part NumberNAND128R3A

NAND128-A

NAND128W3ANAND128R4ANAND128W4ANAND256R3A

NAND256-A

NAND256W3ANAND256R4ANAND256W4ANAND512R3A

NAND512-A

NAND512W3ANAND512R4ANAND512W4ANAND01GR3A

NAND01G-A

NAND01GW3ANAND01GR4ANAND01GW4A

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元器件交易网

NAND128-A, NAND256-A, NAND512-A, NAND01G-A

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1

Figure 1.Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1Table 1.Product List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7

Table 2.Figure 2.Table 3.Figure 3.Figure 4.Figure 5.Figure 6.Figure 7.Figure 8.Figure 9.

Product Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Logic Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9TSOP48 and USOP48 Connections, x8 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10TSOP48 and USOP48 Connections, x16 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10FBGA55 Connections, x8 devices (Top view through package). . . . . . . . . . . . . . . . . . .11FBGA55 Connections, x16 devices (Top view through package). . . . . . . . . . . . . . . . . .12FBGA63 Connections, x8 devices (Top view through package). . . . . . . . . . . . . . . . . . .13FBGA63 Connections, x16 devices (Top view through package). . . . . . . . . . . . . . . . . .14

MEMORY ARRAY ORGANIZATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Bad Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Table 4.Valid Blocks. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15Figure 10.Memory Array Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15SIGNAL DESCRIPTIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Inputs/Outputs (I/O0-I/O7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Inputs/Outputs (I/O8-I/O15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Address Latch Enable (AL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16Command Latch Enable (CL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161616 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .161616VDD Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

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