电子EDA实验报告(5)

PORT(LEFT,RIGHT,BRAKE,NIGHT: IN STD_LOGIC; LP,RP,LR,BRAKE_LED,NIGHT_LED:OUT STD_LOGIC); END ENTITY CTRL;

ARCHITECTURE ONE OF CTRL IS BEGIN

NIGHT_LED<=NIGHT; BRAKE_LED<=BRAKE; PROCESS(LEFT,RIGHT)

VARIABLE TEMP: STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN

TEMP:=LEFT & RIGHT; CASE TEMP IS

WHEN \WHEN \WHEN \WHEN OTHERS => LP<='0'; RP<='0'; LR<='1'; END CASE; END PROCESS;

END ARCHITECTURE ONE;

(3)左边灯控制模块的VHDL源程序(LC.VHD) LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

ENTITY LC IS

PORT(CLK,LP,LR,BRAKE,NIGHT: IN STD_LOGIC; LEDL,LEDB,LEDN: OUT STD_LOGIC); END ENTITY LC;

ARCHITECTURE ONE OF LC IS BEGIN LEDB<=BRAKE; LEDN<=NIGHT; PROCESS(CLK,LP,LR) BEGIN

IF CLK'EVENT AND CLK='1' THEN IF(LR='0') THEN IF(LP='0') THEN LEDL<='0'; ELSE LEDL<='1'; END IF; ELSE LEDL<='0'; END IF; END IF; END PROCESS;

END ARCHITECTURE ONE;

(4)左边灯控制模块的VHDL源程序(RC.VHD) LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY RC IS

PORT(CLK,RP,LR,BRAKE,NIGHT: IN STD_LOGIC; LEDR,LEDB,LEDN: OUT STD_LOGIC); END ENTITY RC;

ARCHITECTURE ONE OF RC IS BEGIN LEDB<=BRAKE; LEDN<=NIGHT; PROCESS(CLK,RP,LR) BEGIN

IF CLK'EVENT AND CLK='1' THEN IF(LR='0') THEN IF(RP='0') THEN LEDR<='0'; ELSE LEDR<='1'; END IF; ELSE

LEDR<='0'; END IF; END IF; END PROCESS;

END ARCHITECTURE ONE; 5）“与门”控制模块

LIBRARY IEEE ;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY AND2A IS

PORT (a, b :IN STD_LOGIC; c : OUT STD_LOGIC ); END ENTITY AND2A;

ARCHITECTURE one OF AND2A IS BEGIN

c <= a AND b ; 6）输出模块

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; ENTITY CD IS

PORT (CLK,LEFT,RIGHT,BRAKE,NIGHT : IN STD_LOGIC; LD1,LD2,LD3,RD1,RD2,RD3

:

OUT

（ END ARCHITECTURE ONE; （STD_LOGIC );

END ENTITY CD;

ARCHITECTURE ONE OF CD IS COMPONENT LC

PORT(CLK,LP,LR,BRAKE,NIGHT: IN STD_LOGIC; LEDL,LEDB,LEDN: OUT STD_LOGIC); END COMPONENT ; COMPONENT RC

PORT(CLK,RP,LR,BRAKE,NIGHT: IN STD_LOGIC; LEDR,LEDB,LEDN: OUT STD_LOGIC); END COMPONENT; COMPONENT SZ

PORT(CLK: IN STD_LOGIC; CP: OUT STD_LOGIC); END COMPONENT; COMPONENT CTRL

PORT(LEFT,RIGHT,BRAKE,NIGHT: IN STD_LOGIC; LP,RP,LR,BRAKE_LED,NIGHT_LED:OUT STD_LOGIC); END COMPONENT ; COMPONENT AND2A

PORT (a, b :IN STD_LOGIC; c : OUT STD_LOGIC );

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