基于FPGA的数字电压表设计(5)

end if;

end case;

end if;

end process; end Behavioral;

adc0809: library IEEE;

use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- Uncomment the following lines to use the declarations that are -- provided for instantiating Xilinx primitive components. --library UNISIM;

--use UNISIM.VComponents.all;

entity ad0809 is

Port ( clk,reset:in std_logic; eoc:in std_logic;

D:in std_logic_vector(7 downto 0); ale,start,oe,clk500k:out std_logic; xs:out std_logic_vector(8 downto 0);

Q:out std_logic_vector(7 downto 0));

end ad0809;

architecture Behavioral of ad0809 is

type state is (st0,st1,st2,st3,st4,st5,st6); signal x:std_logic_vector(8 downto 0); signal current_state,next_state: state ; signal clk500,lock:std_logic;

signal regl:std_logic_vector(7 downto 0); begin

process(clk,reset,clk500) variable count2: integer; variable clk0: std_logic; begin if reset='0' then count2:=0; clk0:='0'; elsif clk'event and clk='1' then count2:=count2+1;

if count2=50 then

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clk0:='1';

elsif count2=100 then count2:=0;clk0:='0';

end if;

end if;

clk500<=clk0; clk500k<=clk0; end process;

process(current_state,eoc) begin

case current_state is

when st0 =>ale<='0';start<='0';oe<='0';lock<='0';x<=\ next_state<=st1;

when st1 =>ale<='1';start<='0';oe<='0';lock<='0';x<=\ next_state<=st2;

when st2 =>ale<='0';start<='1';oe<='0';lock<='0';x<=\ next_state<=st3;

when st3 =>ale<='0';start<='0';oe<='0';lock<='0';x<=\ if eoc='1' then next_state<=st3; else next_state<=st4;

end if;

when st4 =>ale<='0';start<='0';oe<='0';lock<='0';x<=\

if eoc='0' then next_state<=st4; else next_state<=st5;

end if;

when st5 =>ale<='0';start<='0';oe<='1';lock<='0';x<=\ next_state<=st6;

when st6 =>ale<='0';start<='0';oe<='1';lock<='1';x<=\ next_state<=st0;

when others =>ale<='0';start<='0';oe<='0';lock<='0';x<=\ next_state<=st0; end case; end process ;

process(clk500) begin

if rising_edge(clk500) then current_state<=next_state; end if; end process;

process(lock,x) begin

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if lock'event and lock='1'then regl<=D; end if; end process; Q<=regl; xs<=x; end Behavioral;

ym_translate;

-- Xilinx Vhdl produced by program ngd2vhdl F.28

-- Command: -quiet -rpw 100 -tpw 0 -ar Structure -xon true -w -log __projnav/ngd2vhdl.log ym.ngd ym_translate.vhd -- Input file: ym.ngd

-- Output file: ym_translate.vhd -- Design name: ym -- Xilinx: E:/ISE5.2 -- # of Entities: 1 -- Device: 2s100epq208-6

-- The output of ngd2vhdl is a simulation model. This file cannot be synthesized, -- or used in any other manner other than simulation. This netlist uses simulation -- primitives which may not represent the true implementation of the device, however -- the netlist is functionally correct. Do not modify this file.

-- Model for ROC (Reset-On-Configuration) Cell library IEEE;

use IEEE.std_logic_1164.all; use IEEE.VITAL_Timing.all; entity ROC is

generic (InstancePath: STRING := \ WIDTH : Time := 100 ns); port(O : out std_ulogic := '1') ;

attribute VITAL_LEVEL0 of ROC : entity is TRUE; end ROC;

architecture ROC_V of ROC is

attribute VITAL_LEVEL0 of ROC_V : architecture is TRUE; begin

ONE_SHOT : process begin

if (WIDTH <= 0 ns) then assert FALSE report

\ severity failure; else

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wait for WIDTH; O <= '0'; end if; wait;

end process ONE_SHOT; end ROC_V;

-- Model for TOC (Tristate-On-Configuration) Cell library IEEE;

use IEEE.std_logic_1164.all; use IEEE.VITAL_Timing.all; entity TOC is

generic (InstancePath: STRING := \ WIDTH : Time := 0 ns); port(O : out std_ulogic := '0');

attribute VITAL_LEVEL0 of TOC : entity is TRUE; end TOC;

architecture TOC_V of TOC is

attribute VITAL_LEVEL0 of TOC_V : architecture is TRUE; begin

ONE_SHOT : process begin O <= '1';

if (WIDTH <= 0 ns) then O <= '0'; else

wait for WIDTH; O <= '0'; end if; wait;

end process ONE_SHOT; end TOC_V;

library IEEE;

use IEEE.STD_LOGIC_1164.ALL; library SIMPRIM;

use SIMPRIM.VCOMPONENTS.ALL; use SIMPRIM.VPACKAGE.ALL; entity ym is port (

clk : in STD_LOGIC := 'X'; reset : in STD_LOGIC := 'X';

q : in STD_LOGIC_VECTOR ( 7 downto 0 );

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v1 : out STD_LOGIC_VECTOR ( 3 downto 0 ); v2 : out STD_LOGIC_VECTOR ( 3 downto 0 ); v3 : out STD_LOGIC_VECTOR ( 3 downto 0 ); v4 : out STD_LOGIC_VECTOR ( 3 downto 0 ); v5 : out STD_LOGIC_VECTOR ( 3 downto 0 ) ); end ym;

architecture Structure of ym is component ROC

generic (InstancePath: STRING := \ WIDTH : Time := 100 ns); port (O : out STD_ULOGIC := '1'); end component; component TOC

generic (InstancePath: STRING := \ WIDTH : Time := 0 ns); port (O : out STD_ULOGIC := '1'); end component;

signal clk_bufgp : STD_LOGIC; signal reset_ibuf : STD_LOGIC; signal q_5_ibuf : STD_LOGIC; signal q_0_ibuf : STD_LOGIC; signal q_1_ibuf : STD_LOGIC; signal q_4_ibuf : STD_LOGIC; signal q_3_ibuf : STD_LOGIC; signal q_2_ibuf : STD_LOGIC;

signal v44_madd_n0000_inst_cy_1 : STD_LOGIC; signal n1198 : STD_LOGIC; signal choice84 : STD_LOGIC;

signal v44_madd_n0000_inst_cy_2 : STD_LOGIC; signal v33_madd_n0000_inst_cy_1 : STD_LOGIC; signal n1063 : STD_LOGIC; signal q_7_ibuf : STD_LOGIC; signal q_6_ibuf : STD_LOGIC; signal v2_0_obuf : STD_LOGIC; signal v33_0_n33 : STD_LOGIC;

signal v33_madd_n0000_inst_lut2_0 : STD_LOGIC; signal v33_madd_n0000_inst_cy_0 : STD_LOGIC; signal v55_madd_n0000_inst_lut2_0 : STD_LOGIC; signal n290 : STD_LOGIC;

signal v55_madd_n0000_inst_cy_2 : STD_LOGIC; signal v55_madd_n0000_inst_cy_1 : STD_LOGIC; signal v33_madd_n0000_inst_cy_2 : STD_LOGIC;

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