verilog HDL基础程序(5)

div_reg<=0; else begin if(div_reg==div_par-1) div_reg<=0; else div_reg<=div_reg+1; end end

always@(posedge clk)//分频得到8倍波特率的时钟 begin if(!rst) clkbaud8x<=0; else if(div_reg==div_par-1) clkbaud8x<=~clkbaud8x; end

always@(posedge clkbaud8x or negedge rst) begin if(!rst) div8_rec_reg<=0; else if(recstart)//接收开始标志 div8_rec_reg<=div8_rec_reg+1;//接收开始后，时隙数在8倍波特率的时钟下加1循环 end

always@(posedge clkbaud8x or negedge rst) begin if(!rst) div8_tras_reg<=0; else if(trasstart) div8_tras_reg<=div8_tras_reg+1;//发送开始后，时隙数在8倍波特率的时钟下加1循环 end

always@(div8_rec_reg) begin if(div8_rec_reg==7) clkbaud_rec=1;//在第7个时隙，接收使能信号有效，将数据打入 else clkbaud_rec=0; end

always@(div8_tras_reg) begin if(div8_tras_reg==7) clkbaud_tras=1;//在第7个时隙，发送使能信号有效，将数据发出 else clkbaud_tras=0;

end

always@(posedge clkbaud8x or negedge rst) begin if(!rst) begin txd_reg<=1; trasstart<=0; txd_buf<=0; state_tras<=0; send_state<=0; key_entry2<=0; end else begin if(!key_entry2) begin if(key_entry1) begin key_entry2<=1; txd_buf<=8'd50; //\ end end else begin case(state_tras) 4'b0000: begin //发送起始位 if(!trasstart&&send_state<7) trasstart<=1; else if(send_state<7) begin if(clkbaud_tras) begin txd_reg<=0; state_tras<=state_tras+1; end end else begin key_entry2<=0; state_tras<=0; end end 4'b0001: begin //发送第1位 if(clkbaud_tras) begin txd_reg<=txd_buf[0]; txd_buf[6:0]<=txd_buf[7:1]; state_tras<=state_tras+1; end end 4'b0010: begin //发送第2位 if(clkbaud_tras) begin txd_reg<=txd_buf[0];

txd_buf[6:0]<=txd_buf[7:1]; state_tras<=state_tras+1; end end

4'b0011: begin //发送第3位 if(clkbaud_tras) begin txd_reg<=txd_buf[0]; txd_buf[6:0]<=txd_buf[7:1]; state_tras<=state_tras+1; end end

4'b0100: begin //发送第4位 if(clkbaud_tras) begin txd_reg<=txd_buf[0]; txd_buf[6:0]<=txd_buf[7:1]; state_tras<=state_tras+1; end end

4'b0101: begin //发送第5位 if(clkbaud_tras) begin txd_reg<=txd_buf[0]; txd_buf[6:0]<=txd_buf[7:1]; state_tras<=state_tras+1; end end

4'b0110: begin //发送第6位 if(clkbaud_tras) begin txd_reg<=txd_buf[0]; txd_buf[6:0]<=txd_buf[7:1]; state_tras<=state_tras+1; end end

4'b0111: begin //发送第7位 if(clkbaud_tras) begin txd_reg<=txd_buf[0]; txd_buf[6:0]<=txd_buf[7:1]; state_tras<=state_tras+1; end end

4'b1000: begin //发送第8位 if(clkbaud_tras) begin txd_reg<=txd_buf[0]; txd_buf[6:0]<=txd_buf[7:1]; state_tras<=state_tras+1;

end end 4'b1001: begin //发送停止位 if(clkbaud_tras) begin txd_reg<=1; txd_buf<=8'h55; state_tras<=state_tras+1; end end 4'b1111:begin if(clkbaud_tras) begin state_tras<=state_tras+1; send_state<=send_state+1; trasstart<=0; case(send_state) 3'b000: txd_buf<=8'd49;//\ 3'b001: txd_buf<=8'd32;//\ 3'b010: txd_buf<=8'd69;//\ 3'b011: txd_buf<=8'd68;//\ 3'b100: txd_buf<=8'd65;//\ 3'b101: txd_buf<=8'd10;//\ default: txd_buf<=0; endcase end end default: begin if(clkbaud_tras) begin state_tras<=state_tras+1; trasstart<=1; end end endcase end end end

always@(posedge clkbaud8x or negedge rst)//接受PC机的数据 begin

if(!rst) begin rxd_reg1<=0; rxd_reg2<=0; rxd_buf<=0; state_rec<=0; recstart<=0; recstart_tmp<=0; end else begin rxd_reg1<=rxd; rxd_reg2<=rxd_reg1; if(state_rec==0) begin if(recstart_tmp==1) begin recstart<=1; recstart_tmp<=0; state_rec<=state_rec+1; end else if(!rxd_reg1&&rxd_reg2) //检测到起始位的下降沿，进入接受状态 recstart_tmp<=1; end else if(state_rec>=1&&state_rec<=8) begin if(clkbaud_rec) begin rxd_buf[7]<=rxd_reg2; rxd_buf[6:0]<=rxd_buf[7:1]; state_rec<=state_rec+1; end end else if(state_rec==9) begin if(clkbaud_rec) begin state_rec<=0; recstart<=0; end end end end

always@(rxd_buf) //将接受的数据用数码管显示出来 begin

case (rxd_buf) 8'h30: seg_data=8'b11000000; 8'h31: seg_data=8'b11111001; 8'h32: seg_data=8'b10100100;

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