IAR中cortex-m4启动流程分析(4)

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// Set system options dividers

//MCG=PLL, core = MCG, bus = MCG/2, FlexBus = MCG/2, Flash clock= MCG/4 set_sys_dividers(0,1,1,3);

// Set the VCO divider and enable the PLL for 96MHz, LOLIE=0, PLLS=1, CME= MCG_C6 = MCG_C6_PLLS_MASK | MCG_C6_VDIV(24); //VDIV = 24 (x48) pll_freq = 96;

0, VDIV=24

while (!(MCG_S & MCG_S_PLLST_MASK)){}; // wait for PLL status bit to set

while (!(MCG_S & MCG_S_LOCK_MASK)){}; // Wait for LOCK bit to set

// Now running PBE Mode

// Transition into PEE by setting CLKS to 0 // CLKS=0, FRDIV=3, IREFS=0, IRCLKEN=0, IREFSTEN=0 MCG_C1 &= ~MCG_C1_CLKS_MASK;

// Wait for clock status bits to update

while (((MCG_S & MCG_S_CLKST_MASK) >> MCG_S_CLKST_SHIFT) != 0x3){};

// Now running PEE Mode

return pll_freq;

最后，系统运行在PEE模式下。

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