3-8译码器的VHDL设计(2)

OA_MORE_THAN_B<='0';OB_MORE_THAN_A<='1';OA_EQUAL_B<='0';

ELSIF(A(0)>B(0))THEN

OA_MORE_THAN_B<='1';OB_MORE_THAN_A<='0';OA_EQUAL_B<='0';

ELSIF(A(0)

OA_MORE_THAN_B<='0';OB_MORE_THAN_A<='1';OA_EQUAL_B<='0';

ELSE

——如果输入中两个数相等的标志位为0，则表明高位不相等，停止比较，输出结果。

OA_MORE_THAN_B<='0';OB_MORE_THAN_A<='0';OA_EQUAL_B<='1';

END IF;

ELSE

OA_MORE_THAN_B<=IA_MORE_THAN_B;OB_MORE_THAN_A<=IB_MORE_THAN_A;

OA_EQUAL_B<=IA_EQUAL_B;

END IF;

END PROCESS;

END BEHAV;

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY comparator IS PORT ( CLK : IN STD_LOGIC;

SIN : IN STD_LOGIC_VECTOR (3 DOWNTO 0); SJ : IN STD_LOGIC_VECTOR (3 DOWNTO 0); Q : OUT STD_LOGIC); END comparator;

ARCHITECTURE behave OF comparator IS SIGNAL SIN1 : INTEGER RANGE 0 TO 15; SIGNAL SJ1 : INTEGER RANGE 0 TO 15; BEGIN

SIN1<= CONV_INTEGER(SIN); SJ1<= CONV_INTEGER(SJ); PROCESS(CLK ) BEGIN

IF (CLK'EVENT AND CLK = '1') THEN IF SIN1

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