EDA四位十进制频率计课程设计报告(4)

when \when \when others =>null; end case;

end process p1;

p2: process(clk) ---计数模块扫描时钟发生器

begin ---时钟信号clk有效上升沿时，cnt8开始计数 if clk'event and clk='1' then cnt8<=cnt8+1; end if;

end process p2;

p3: process(q) ---译码模块 begin

case q(3 downto 0) is ---通过q的值来选择sg的 led地址的已译码数据 when \when \when \when \when \when \when \when \when \when \when others =>null; end case;

end process p3; end one; 分频的主要源程序：

Library ieee;

Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Entity count is

Port(clk50:in std_logic; ---端口定义 qlk:out std_logic); End count;

Architecture one of count is Begin

HZ:process(clk50)

Variable cout:integer:=0; ---设置变量cout，且其初值为0

Begin

If clk50'event and clk50='1' then ---时钟信号clk50上升沿时，cout值就增1 cout:=cout+1;

If cout<=24999 then qlk<='0'; ---cout<=249999时，qlk置0

Else if cout<=49999 then qlk<='1'; ---2499949999时，cout值清零 End if; End if; End if;

End process HZ; End one; 动态显示源程序；

Library ieee;

Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Entity export is

Port(q2:in std_logic; ---端口定义

bt:in std_logic_vector(1 downto 0); sg:in std_logic_vector(6 downto 0 );

led0,led1,led2,led3:out std_logic_vector(6 downto 0)); End;

Architecture one of export is Begin

Process(q2) Begin

If q2'event and q2='1' then ---当q2为上升沿时，通过bt的值来选择sg， Case bt is ---把sg的值赋给相应的led When \When \When \When \When others=>null; End case; end if;

End process; End one;

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