格雷码设计报告(3)

8.附录

附录一 modelsim仿真程序 ①rtl文件

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity geleima is port (

g : in std_logic_vector(3 downto 0);

yout,sg0,sg1,sg2,sg3 : out std_logic_vector(6 downto 0)); end geleima;

architecture rtl of geleima is

signal b:std_logic_vector(3 downto 0); signal q:std_logic_vector(6 downto 0); begin

process (g) begin

case g is

when \ when \ when \ when \ when \ when \ when \ when \ when \ when \ when \ when \ when \ when \ when \ when \ when others=>null; end case ; end process; yout<=q;

p1:process(g) begin

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case g is

when \ when \ when \ when \ when \ when \ when \ when \ when \ when \ when \ when \ when \ when \ when \ when \ when others =>NULL; end case;

end process p1; p2: process(b) begin

case b is

when \sg3 <= \<= \<= \<= \

when \sg3 <= \<= \<= \<= \

when \sg3 <= \<= \<= \<= \

when \sg3 <= \<= \<= \<= \

when \sg3 <= \<= \<= \<= \

when \sg3 <= \<= \<= \<= \

when \sg3 <= \<= \<= \<= \

when \sg3 <= \<= \<= \<= \

when \sg3 <= \<= \<= \<= \

when \sg3 <= \<= \<= \<= \

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when \sg3 <= \<= \<= \<= \

when \sg3 <= \<= \<= \<= \

when \sg3 <= \<= \<= \<= \

when \sg3 <= \<= \<= \<= \

when \sg3 <= \<= \<= \<= \

when \sg3 <= \<= \<= \<= \

when others =>null; end case;

end process p2; end rtl;

②testbench文件

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity test is end test;

architecture behaviour of test is

signal sig_g :std_logic_vector(3 downto 0):= \signal sig_yout :std_logic_vector(6 downto 0); signal sig_sg0:std_logic_vector(6 downto 0); signal sig_sg1:std_logic_vector(6 downto 0); signal sig_sg2:std_logic_vector(6 downto 0); signal sig_sg3:std_logic_vector(6 downto 0); component geleima port (

g : in std_logic_vector(3 downto 0);

yout,sg0,sg1,sg2,sg3: out std_logic_vector(6 downto 0)); end component; begin

-- instance

u_geleima : geleima port map ( g => sig_g,

yout => sig_yout, sg0=> sig_sg0, sg1=> sig_sg1, sg2=> sig_sg2, sg3=> sig_sg3);

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sig_g <= \ns, \after 40 ns,\after 50 ns, \after 60 ns,\after 70 ns, \80 ns,\after 90 ns, \100 ns,\after 110 ns, \ns ,\end behaviour;

附录二 测试结果图

In---0101 Out---0111

In---0010 Out---0011

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In---1010 Out---1111

In---1000 Out---1100

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