实验四 多位十进制计数器的设计与实现

实验四 多位十进制计数器的设计与实现（4 课时）

实验目的

1.熟练掌握设计电路下载到芯片的关键设置与基本步骤和利用实验箱上的输入信号和输出显示器件在线测试设计电路的方法。

2.学习使用 VHDL 语言设计多位计数器和 7 段译码电路的方法。

3.学习多位数码管的动态显示原理，掌握数码管驱动电路灵活设计方法。 实验原理

1.米字形数码管（共阴）

笔画接口：A1、A2、B、C、D1、D2、E、F、G、H、J、K、M、N、O、P、DP 位选接口：sel0,sel1,sel2,sel3.

sel0 Sel1 Sel2 Sel3 选中的数码管 0 1 1 1 第 4 位 1 0 1 1 第 3 位 1 1 0 1 第 2 位

1 1 1 0 第 1 位（右） 2. 8 位 7 段数码管（共阴）

笔画接口：a、b、c、d、e、f、g、dp 位选接口：sel0,sel1,sel2,sel3(可不用). Sel2 Sel1 Sel0 选中点亮的数码管 1 1 1 第 1 位（最右） 1 1 0 第 2 位 1 0 1 第 3 位 1 0 0 第 4 位 0 1 1 第 5 位 0 1 0 第 6 位 0 0 1 第 7 位 0 0 0 第 8 位 实验内容与要求

1.设计一个十进制计数器，具有显示位置随计数时钟在八个数码管中左右滚动的功能。（6 分）

2.设计一个符号显示电路，使其通过米字型数码管显示至少四页的自定义英文和数字符号。（每页 4 个字符）（3 分）

3.设计一个 4 位十进制计数器，具有加减计数功能和置数功能，并能通过数码管显示计数结果。减数为零时发声报警。（3 分） 1：library IEEE;

use IEEE.std_logic_1164.all; use IEEE.Std_logic_unsigned.all; entity cnt10 is port (

clk : in std_logic;

data_out : out std_logic_vector (7 downto 0); selout: out std_logic_vector (2 downto 0)); end entity;

architecture art1 of cnt10 is

begin

process(clk)

variable cnt1:integer range 0 to 9; begin

if clk'event and clk='1' then cnt1:=cnt1+1; if cnt1>9 then cnt1:=0; end if; end if;

case cnt1 is

when 0 => data_out <= \when 1 => data_out <= \when 2 => data_out <= \when 3 => data_out <= \when 4 => data_out <= \when 5 => data_out <= \when 6 => data_out <= \when 7 => data_out <= \when 8 => data_out <= \when 9 => data_out <= \when others => NULL; end case; end process; process(clk)

variable cntsel:integer range 0 to 13; begin

if clk'event and clk='1' then cntsel:=cntsel+1; if cntsel>13 then cntsel:=0; end if; end if;

case cntsel is

when 0 => selout <= \ when 1 => selout <= \ when 2 => selout <= \when 3 => selout <= \when 4 => selout <= \when 5 => selout <= \when 6 => selout <= \when 7 => selout <= \when 8 => selout <= \ when 9 => selout <= \

when others => NULL; end case; end process; end art1;

2：Library IEEE;

Use ieee.std_logic_1164.all; Use ieee.std_logic_unsigned.all; Entity miguan is

port( clk : in std_logic; WX : out std_logic_vector (3 downto 0); DX : out std_logic_vector (15 downto 0)); End entity miguan;

Architecture bhv of miguan is Type state is(st0,st1,st2,st3); Signal current_state:state :=st0; Signal next_state:state;

Signal shu1 : integer range 0 to 3;

Signal shu2 : std_logic_vector(13 downto 0); Signal A,B,C,D:std_logic_vector(15 DOWNTO 0); Begin

process (clk) is Begin

If (clk'event and clk='1') then shu2<=shu2+\ If shu2=\ current_state<=NEXT_STATE; else current_state<=current_state; End if; End if;

End process;

Process (current_state) Begin

Case current_state is when

st0=>A<=\ B<=\ C<=\ D<=\ NEXT_STATE<=ST1; when

st1=>A<=\ B<=\ C<=\

D<=\ NEXT_STATE<=ST2; when

st2=>A<=\ B<=\ C<=\ D<=\ NEXT_STATE<=st3; when

st3=>A<=\ B<=\ C<=\ D<=\ NEXT_STATE<=ST0; End case; End process; Process (clk) is Begin

if rising_edge(clk) then if shu1>3 then shu1<=0; else shu1<=shu1+1; end if; case shu1 is WHEN 0 =>WX<=\ WHEN 1 =>WX<=\ WHEN 2 =>WX<=\ WHEN 3 =>WX<=\ End case; End if;

End process;

End architecture bhv; 3：library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all;

entity wybcount4 is port(count_clk,saopin_clk,en,load,reset,add_sub:in std_logic; data_in3:in std_logic_vector(3 downto 0);--Left1 data_in2:in std_logic_vector(3 downto 0); data_in1:in std_logic_vector(3 downto 0); data_in0:in std_logic_vector(3 downto 0);--Right1

duanxuan:out std_logic_vector(7 downto 0);--duan xuan sel:out std_logic_vector(1 downto 0);--wei xuan bell:out std_logic); end entity wybcount4;

architecture beh of wybcount4 is constant num0:std_logic_vector:=\ constant num1:std_logic_vector:=\ constant num2:std_logic_vector:=\ constant num3:std_logic_vector:=\ constant num4:std_logic_vector:=\ constant num5:std_logic_vector:=\ constant num6:std_logic_vector:=\ constant num7:std_logic_vector:=\ constant num8:std_logic_vector:=\ constant num9:std_logic_vector:=\ function number(x:std_logic_vector) return std_logic_vector is begin case x is when \ when \ when \ when \ when \ when \ when \ when \ when \ when \ when others =>return \ end case; end number; signal Q3:std_logic_vector(3 downto 0);--zhong jian zhi signal Q2:std_logic_vector(3 downto 0); signal Q1:std_logic_vector(3 downto 0); signal Q0:std_logic_vector(3 downto 0); begin process(count_clk,reset,en,load,add_sub) is begin --counter10 IF reset = '0' THEN

Q0<=(OTHERS => '0'); Q1<=(OTHERS => '0'); Q2<=(OTHERS => '0'); Q3<=(OTHERS => '0');

ELSIF rising_edge(count_clk) THEN if en='0' then if load='0' then Q0<=data_in0; Q1<=data_in1; Q2<=data_in2; Q3<=data_in3; elsif add_sub='0' then--add Q0<=Q0+1; if Q0>=9 then Q0<=\ if Q1>=9 then Q1<=\ if Q2>=9 then Q2<=\ if Q3>=9 then Q3<=\ end if; end if; end if; end if; else--sub Q0<=Q0-1; if Q0<=0 then Q0<=\ if Q1<=0 then Q1<=\ if Q2<=0 then Q2<=\ if Q3<=0 then Q3<=\ end if; end if; end if; end if; end if; end if; END IF;

if (Q0=\ bell<='1';

else bell<='0'; end if; end process; process(saopin_clk) is--sao pin xian shi variable qq:std_logic_vector(0 to 1); begin if (saopin_clk'event and saopin_clk='1') then if qq<=3 then qq:=qq+1; else qq:=\ end if; end if; case qq is when \ when \ when \ when \ end case; end process; end architecture beh;

百度搜索“77cn”或“免费范文网”即可找到本站免费阅读全部范文。收藏本站方便下次阅读，免费范文网，提供经典小说综合文库实验四 多位十进制计数器的设计与实现在线全文阅读。