EDA实验报告完结版(3)

entity schk is

port(din,clk,clr:in std_logic;

ab:out std_logic_vector(1 downto 0)); end schk;

architecture behav of schk is

signal d:std_logic_vector(7 downto 0); signal q:integer range 0 to 8;

type fsm_st is(s0,s1,s2,s3,s4,s5,s6,s7,s8); signal current_state,next_state:fsm_st; begin

d<=\ reg:process(clr,clk) begin

if clr='1' then current_state<=s0; elsif clk='1' and clk'event then current_state<=next_state; end if; end process;

com:process(current_state,din) begin

case current_state is when s0=>q<=0;

if din='0' then next_state<=s0; else next_state<=s1; end if; when s1=>q<=1;

if din='1' then next_state<=s0; else next_state<=s2; end if;

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when s2=>q<=2;

if din='1' then next_state<=s0; else next_state<=s3; end if;

when s3=>q<=3;

if din='1' then next_state<=s0; else next_state<=s4; end if; when s4=>q<=4;

if din='0' then next_state<=s0; else next_state<=s5; end if; when s5=>q<=5;

if din='0' then next_state<=s0; else next_state<=s6; end if; when s6=>q<=6;

if din='0' then next_state<=s0; else next_state<=s7; end if; when s7=>q<=7;

if din='1' then next_state<=s0; else next_state<=s8; end if; when s8=>q<=8; next_state<=s0; end case; end process;

process(q)

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begin

if q=8 then ab<=\ else ab<=\ end if; end process; end behav; 2、实验仿真：

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