五人多数表决器(9)

附录二

选题二 数字式竞赛抢答器设计

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity four is

port(CLK1,EN1,KAISHI:in std_logic;

A,B,C,D:in std_logic; ---------QDJB

A1,B1,C1,D1,RING:out std_logic;

STATES:out std_logic_vector(3 DOWNTO 0);

RST1: IN STD_LOGIC;

ADD: IN STD_LOGIC;

CHOS:IN STD_LOGIC_VECTOR(3 DOWNTO 0); ------JFQ

AA2,AA1,AA0,BB2,BB1,BB0: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

CC2,CC1,CC0,DD2,DD1,DD0: OUT STD_LOGIC_VECTOR(3 DOWNTO 0);

AIN4:IN STD_LOGIC_VECTOR(3 DOWNTO 0);

DOUT7:OUT STD_LOGIC_VECTOR(6 DOWNTO 0)); --------YMQ

end entity four;

architecture one of four is

signal sinor,ringf,tmp,two:std_logic; ---------QDJB.VHD

signal cnt:std_logic_vector(5 DOWNTO 0);

-----------------------------------------------

begin

sinor<=(A XOR B)XOR(C XOR D); --------QDJB.VHD

two<=A and B;

p1:process(A,B,C,D,KAISHI,tmp)

begin

if KAISHI='1' then

tmp<='1';STATES<="0000";

elsif tmp='1' then

if (A='1'AND B='0'AND C='0'AND D='0' ) then

A1<='1'; B1<='0'; C1<='0'; D1<='0'; STATES<="0001";

tmp<='0';

ELSIF (A='0'AND B='1'AND C='0'AND D='0') THEN

A1<='0'; B1<='1'; C1<='0'; D1<='0';STATES<="0010";tmp<='0';

ELSIF (A='0'AND B='0'AND C='1'AND D='0') THEN

A1<='0'; B1<='0'; C1<='1'; D1<='0'; STATES<="0011"; tmp<='0';

ELSIF (A='0'AND B='0'AND C='0'AND D='1') THEN

A1<='0'; B1<='0'; C1<='0'; D1<='1'; STATES<="0100";tmp<='0';

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