基于FPGA乒乓球游戏机Verilog设计(2)

乒乓球游戏机核心控制模块：

module led_con(clk_1s,reset,start,key_a,key_b,led_pose,sum,score_a,score_b,speaker,led);

input clk_1s; input reset; input start; input key_a; input key_b; input led_pose; output[4:0] sum; output[3:0] score_a; output[3:0] score_b; output[5:0] led; output speaker; reg speaker;

//-------------------------------------------------------------- reg[5:0] led_move; reg[3:0] score_a_r; reg[3:0] score_b_r; reg[6:0] state;

parameter[6:0] s0 = 7'b0000001, s1 = 7'b0000010, s2 = 7'b0000100, s3 = 7'b0001000, s4 = 7'b0010000, s5 = 7'b0100000, s6 = 7'b1000000;

always @(posedge clk_1s or negedge reset) begin

if(!reset) state <= s0; else

if(!start)

begin case(state) s0: begin speaker <= 1; if(score_a_r == 4'd11 || score_b_r == 4'd11) begin score_a_r <= 4'b0; score_b_r <= 4'b0; end else if(!led_pose) begin led_move <= 6'b011111; state <= s1; end else if(led_pose) begin led_move <= 6'b111110; state <= s4; end end s1: begin if(!key_a) begin led_move <= {led_move[0],led_move[5:1]}; state <= s2; end else if(!key_b) begin speaker <= 0; state <= s0; end else state <= s1; end s2: begin if((led_move[2] == 0 || led_move[1] == 0 || led_move[0] == 0) && !key_b) state <= s6; else if(((led_move[2] == 0 || led_move[1] == 0) && key_b) ||(led_move[5] == 0 || led_move[4] == 0 || led_move[3] == 0)) state <= s3; else begin score_a_r <= score_a_r+1;

s3: s4:

state <= s0; end end

begin

led_move <= {led_move[0],led_move[5:1]}; state <= s2; end

begin

if(!key_b) begin led_move <= {led_move[4:0],led_move[5]}; state <= s5; end

else if(!key_a) begin speaker <= 0; state <= s0; end else state <= s4; end

s5: begin if((led_move[3] == 0 || led_move[4] == 0 || led_move[5] == 0) && !key_a) state <= s3; else if(((led_move[3] == 0 || led_move[4] == 0) && key_a) ||(led_move[0] == 0 || led_move[1] == 0 || led_move[2] == 0)) state <= s6; else begin score_b_r <= score_b_r+1; state <= s0; end end s6: begin led_move <= {led_move[4:0],led_move[5]}; state <= s5; end default:state <= s0; endcase end else begin

led_move <= 6'b110011; speaker <= 1; end end

assign score_a = score_a_r; assign score_b = score_b_r; assign led = led_move;

assign sum = score_a_r+score_b_r; endmodule

基于 FPGA乒乓球比赛游戏机顶层原理图

后记：因为时间关系，资料没有整理的很理顺，请大家谅解，整个工程会给出，在板子上已调试成功，因为乒乓球位置控制模块所用的时钟为clk_1000ms,所以按键停留最好

超过1s就能更稳的接住球。程序有点乱，没有优化，仅供参考！！

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