基于FPGA的红外线型学习遥控器(2)

4设计成果展示

硬件完整电路图片以及操作视频

（视频在文件夹里）

5总结

通过本次设计一个实用的万能遥控器，我们对课题设计的完整流程有了深入的认识，包括项目的选择、资料的收集、元件购买、PCB板的绘制投板、模块程序设计以及报账流程等，最主要的是因为我们的设计程序在网上的相关资料很少，所以我们是自己根据要实现的功能尝试着自己写程序，自己调试，受益匪浅，不仅很好地巩固和理解了课堂理论知识，更为以后做项目参加比赛等积累了很好的经验。同时，4人小组的合作也很成功，经过这次设计懂得了团队协作和正确分工的重要性！

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6元件清单

名称 贴片电阻 贴片电容 S9013三极管 IR5308C-C-45 HL-A838 排针1*3

数量 150 100 20 20 20 30 单价/元 0.15 0.24 1.85 1.85 3.7 1.85 总计/元 22.5 24 37 37 74 55.5 250 附录

去抖动程序 LIBRARY ieee;

USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY hw_qd IS

PORT(clk : IN STD_LOGIC ; kin : IN STD_LOGIC ; kout : OUT STD_LOGIC); END ENTITY;

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ARCHITECTURE behav OF hw_qd IS SIGNAL kh,kl:std_logic_vector(3 downto 0); BEGIN

PROCESS(kin, clk) BEGIN

if rising_edge(clk) then if (kin='0') then kl<=kl+1; else kl<=\if; end if; END PROCESS ; PROCESS(kin, clk) BEGIN

if rising_edge(clk) then if (kin='1') then kh<=kh+1; else kh<=\if; end if; END PROCESS ; PROCESS(clk,kh,kl) BEGIN

if rising_edge(clk) then if (kh>\then kout<='1'; elsif (kl>\then kout<='0'; end if; end if; END PROCESS ; END behav;

红外接收程序

library ieee;

use ieee.std_logic_1164.all; entity hw_InfraredPort is port(CLK:in std_logic;--50MHz RST:in std_logic; IRIN:in std_logic; RD:in std_logic; CS:in std_logic; led:out std_logic;

DATA:out std_logic_vector(31 downto 0)); end entity hw_InfraredPort;

architecture one of hw_InfraredPort is type state is(s0,s1,s2,s3,s4); signal sta:state;

signal vData:std_logic_vector(31 downto 0); signal clk_1m:std_logic; --1MHz begin

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process(CLK)

variable clk_counter:integer range 0 to 25; begin

if(CLK'event and CLK='1')then clk_counter:=clk_counter+1; if(clk_counter=25)then clk_counter:=0; clk_1m<=not clk_1m; end if; end if; end process; process(RST,CLK)

variable step:integer range 0 to 32; variable counter:integer range 0 to 10000; begin

if(RST='0')then sta<=s0;

vData<=X\led<='0';

elsif(clk_1m'event and clk_1m='1')then case sta is when s0=>led<='0'; counter:=0; if(IRIN='0')then sta<=s1; end if;

when s1=>led<='0'; if(IRIN='0')then counter:=counter+1;

elsif(counter>3200)then --time(9ms) > 3.2ms sta<=s2; counter:=0; else sta<=s0; end if;

when s2=>led<='0'; if(IRIN='1')then counter:=counter+1;

if(counter>8000)then --time(4.5ms) > 8ms,back to begin sta<=s0; end if;

elsif(counter<8000)then --time(4.5ms) < 8ms,continue

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sta<=s3; counter:=0; step:=0; else sta<=s0; end if;

when s3=>led<='1'; if(IRIN='0')then counter:=counter+1;

elsif(counter<1600)then --time(0.56ms)<1.6ms,continue sta<=s4; counter:=0; else sta<=s0; end if;

when s4=>led<='1'; if(IRIN='1')then counter:=counter+1;

if(counter>3200)then --time(1.12ms)>3.2ms,back to begin sta<=s0; DATA<=vData; end if; else

if(counter>800)then --time>0.8ms,get the data 1 vData(step)<='1'; else

vData(step)<='0'; --time<0.8ms,get the data 0 end if; step:=step+1; sta<=s3; counter:=0; end if; end case; end if; end process;

end architecture one; 存储写入程序：

library ieee;

use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity hw_address is port(clk:in std_logic;

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