VHDL设计的12进制可调时钟带闹铃功能 - 图文(3)

architecture one of display is

signal sc_l,sc_h,min_l,min_h,hour_l,hour_h:integer range 0 to 9;

signal sc_l_q,sc_h_q,min_l_q,min_h_q,hour_l_q,hour_h_q: std_logic_vector(7

downto 0);

begin

process(sc_data,min_data,hour_data) --将时分秒的十位和各位分开 begin

sc_l<=sc_data mod 10; sc_h<=integer(sc_data/10); min_l<=min_data mod 10; min_h<=integer(min_data/10); hour_l<=hour_data mod 10; hour_h<=integer(hour_data/10); end process;

process(sc_l,sc_h,min_l,min_h,hour_l,hour_h) 转换成数码管显示的段码

begin

case(sc_l)is --秒各位 when 0 => sc_l_q<=\ when 1 => sc_l_q<=\ when 2 => sc_l_q<=\ when 3 => sc_l_q<=\ when 4 => sc_l_q<=\ when 5 => sc_l_q<=\ when 6 => sc_l_q<=\ when 7 => sc_l_q<=\ when 8 => sc_l_q<=\ when 9 => sc_l_q<=\ when others=>null; end case;

case(sc_h)is --秒十位 when 0 => sc_h_q<=\ when 1 => sc_h_q<=\ when 2 => sc_h_q<=\ when 3 => sc_h_q<=\ when 4 => sc_h_q<=\ when 5 => sc_h_q<=\

when others=>null; end case;

--将时分秒的个位和十位

case(min_l)is --分个位 when 0 => min_l_q<=\ when 1 => min_l_q<=\ when 2 => min_l_q<=\ when 3 => min_l_q<=\ when 4 => min_l_q<=\ when 5 => min_l_q<=\ when 6 => min_l_q<=\ when 7 => min_l_q<=\ when 8 => min_l_q<=\ when 9 => min_l_q<=\ when others=>null; end case;

case(min_h)is --分十位 when 0 => min_h_q<=\ when 1 => min_h_q<=\ when 2 => min_h_q<=\ when 3 => min_h_q<=\ when 4 => min_h_q<=\ when 5 => min_h_q<=\

when others=>null; end case;

case(hour_l)is --时个位 when 0 => hour_l_q<=\ when 1 => hour_l_q<=\ when 2 => hour_l_q<=\ when 3 => hour_l_q<=\ when 4 => hour_l_q<=\ when 5 => hour_l_q<=\ when 6 => hour_l_q<=\ when 7 => hour_l_q<=\ when 8 => hour_l_q<=\ when 9 => hour_l_q<=\ when others=>null; end case;

case(hour_h)is --时十位 when 0 => hour_h_q<=\ when 1 => hour_h_q<=\ when others=>null;

end case; end process;

process(flag_1khz) --此进程是实现数码管动态显示 variable counter_10:integer range 0 to 10; begin

if(flag_1khz 'event and flag_1khz='1') then if(counter_10=7) then counter_10:=0; else

counter_10:=counter_10+1; end if; end if;

case (counter_10)is when 0 => S<=\ when 1 => S<=\ when 2 => S<=\

--显示'-'

when 3 => S<=\ when 4 => S<=\ when 5 => S<=\

--显示'-'

when 6 => S<=\ when 7 => S<=\ when others=>null; end case; end process; end architecture one;

4、 硬件仿真如下：

百度搜索“77cn”或“免费范文网”即可找到本站免费阅读全部范文。收藏本站方便下次阅读，免费范文网，提供经典小说综合文库VHDL设计的12进制可调时钟带闹铃功能 - 图文(3)在线全文阅读。