代码1 功能1

代码1 功能:通过sw控制LED灯 module test001(SW,LEDR,LEDG); input[17:0] SW;//sw[17] output[17:0] LEDR; output reg[7:0] LEDG; //assign LEDRG[7:3]=5'B00000; assign LEDR=SW; always@(SW) begin

case(SW[17:15]) 3'b000:LEDG=SW[2:0]; 3'b001:LEDG=SW[5:3]; 3'b010:LEDG=SW[8:6]; 3'b011:LEDG=SW[11:9]; 3'b100:LEDG=SW[14:12]; default:LEDG=8'B00000000; endcase end endmodule

代码2: sw输入两个8位数,乘积在7段管上显示

module test004(SW,HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7); input[17:0] SW;

output[6:0] HEX0,HEX1,HEX2,HEX3,HEX4,HEX5,HEX6,HEX7; wire[15:0] mult;

assign mult=SW[15:8]*SW[7:0]; assign

{HEX7,HEX6,HEX5,HEX4}={decodeout(SW[7:4]),decodeout(SW[3:0]),decodeout(SW[15:12]),decodeout(SW[11:8])};

assign

{HEX3,HEX2,HEX1,HEX0}={decodeout(mult[15:12]),decodeout(mult[11:8]),decodeout(mult[7:4]),decodeout(mult[3:0])};

function[6:0] decodeout;

input[3:0] ina; case(ina)

4'b0000:decodeout=7'b1000000;//0 4'b0001:decodeout=7'b1111001; 4'b0010:decodeout=7'b0100100; 4'b0011:decodeout=7'b0110000; 4'b0100:decodeout=7'b0011001; 4'b0101:decodeout=7'b0010010; 4'b0110:decodeout=7'b0000010; 4'b0111:decodeout=7'b1111000; 4'b1000:decodeout=7'b0000000; 4'b1001:decodeout=7'b0010000;//9 4'b1010:decodeout=7'b0001000;//a 4'b1011:decodeout=7'b0000011;//b 4'b1100:decodeout=7'b1000110;//c 4'b1101:decodeout=7'b0100001;//d 4'b1110:decodeout=7'b0000110;//e 4'b1111:decodeout=7'b0001110;//f default:decodeout=7'b1111111; endcase endfunction endmodule

代码3:sw输入16位数,以十进制在7段管上显示

module test003(SW,HEX7,HEX6,HEX5,HEX4,HEX3,HEX2,HEX1,HEX0); input[17:0] SW;

output[6:0] HEX7,HEX6,HEX5,HEX4,HEX3,HEX2,HEX1,HEX0; assign HEX0=decodeout(SW'd10); assign HEX1=decodeout((SW/18'd10)'d10); assign HEX2=decodeout((SW/18'd100)'d10); assign HEX3=decodeout((SW/18'd1000)'d10); assign HEX4=decodeout((SW/18'd10000)'d10); assign HEX5=decodeout((SW/18'd100000)'d10);

assign HEX6=decodeout((SW/28'd1000000)'d10); assign HEX7=decodeout((SW/28'd10000000)'d10); function[6:0] decodeout; input[3:0] indec;

case(indec) //用case语句进行译码 4'd0:decodeout=7'b1000000; 4'd1:decodeout=7'b1111001; 4'd2:decodeout=7'b0100100; 4'd3:decodeout=7'b0110000; 4'd4:decodeout=7'b0011001; 4'd5:decodeout=7'b0010010; 4'd6:decodeout=7'b0000010; 4'd7:decodeout=7'b1111000; 4'd8:decodeout=7'b0000000; 4'd9:decodeout=7'b0010000; default: decodeout=7'b1111111; endcase endfunction endmodule

代码4:sw控制hello显示

module test002(SW,HEX0,HEX1,HEX2,HEX3,HEX4); input[17:0] SW;

output reg[6:0] HEX0,HEX1,HEX2,HEX3,HEX4; always@(SW) begin

case(SW[17:15])

3'b000:{HEX4,HEX3,HEX2,HEX1,HEX0}=35'B0001001_0000110_1000111_1000111_1000000;

3'b001:{HEX4,HEX3,HEX2,HEX1,HEX0}=35'B0000110_1000111_1000111_1000000_0001001;

3'b010:{HEX4,HEX3,HEX2,HEX1,HEX0}=35'B1000111_1000111_1000000_0001001_0000110;

3'b011:{HEX4,HEX3,HEX2,HEX1,HEX0}=35'B1000111_1000000_0001001_0000110_1000111;

3'b100:{HEX4,HEX3,HEX2,HEX1,HEX0}=35'B1000000_0001001_0000110_1000111_1000111;

default:{HEX4,HEX3,HEX2,HEX1,HEX0}=35'B1111111_1111111_1111111_1111111_1111111;

endcase end endmodule

代码5:状态机检测101序列,注意此代码使用3个状态实现,与课本上四状态有区别 module test0002(clk,clr,x,z); input clk,clr,x; output reg z;

reg[1:0] state,next_state;

parameter s0=2'b00,s1=2'b01,s2=2'b10; always@(posedge clk or posedge clr) begin

if(clr) state<=s0; else state<=next_state; end

always@(state or x) begin case(state)

s0:if(x) next_state<=s1;else next_state<=s0; s1:if(x) next_state<=s1;else next_state<=s2; s2:if(x) next_state<=s1;else next_state<=s0; endcase end

always@(state or x) begin case(state)

s2:if(x) z=1;else z=0; default:z=0;

endcase //else // case(state)

// s0:begin if(x) state<=s1;else state<=s0;z=0; end // s1:begin if(x) state<=s1;else state<=s2;z=0; end

// s2:begin if(x) begin state<=s1;z=1;end else begin state<=s0;z=0;end end // default:begin state<=s0;z=0; end // endcase end endmodule

代码6:运算器任务方式实现 module alutask(opcode,a,b,c); input[1:0] opcode; input[7:0] a,b; output reg[8:0] c; always@(a or b or opcode) begin//always case(opcode) 2'b00:my_and(a,b,c); 2'b01:c=a|b; 2'b10:c=a-b; 2'b11:c=a+b; default:c=9'bx; endcase end//always

task my_and; input[7:0] my_a,my_b; output[7:0] my_c; integer i; for(i=0;i<=7;i=i+1)

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