Verilog的D触发器及JK触发器实验

module JKchufa(set,clr,clk,j,k,q3,q3_); input set,clr,clk,j,k; output q3,q3_; reg q3,q3_;

always@(set or clr) begin

if(set==1) begin q3<=1; q3_<=0; end

else if(set==0&clr==1) begin q3<=0; q3_<=1; end end

always@(negedge clk) begin

if(j==1&k==0&set==0&clr==0) begin

q3<=1;q3_<=0; end

else if(j==0&k==1&set==0&clr==0) begin

q3<=0;q3_<=1; end

else if(j==1&k==1&set==0&clr==0) begin

q3<=!q3;q3_<=!q3_; end end

endmodule

module Dchufa(set,clr,clk,d,q2,q2_); input set,clr,clk,d; output q2,q2_; reg q2,q2_;

always@(set or clr) begin

if(set==1) begin q2<=1; q2_<=0; end

else if(set==0&clr==1) begin q2<=0; q2_<=1; end end

always@(posedge clk) begin

if(d==0&set==0&clr==0) begin

q2<=0;q2_<=1; end

else if(d==1&set==0&clr==0) begin

q2<=1;q2_<=0; end end

endmodule

测试程序

`timescale 1ns/100ps `include \`include \`include \

module tb_chufa;

reg s,r,d,j,k,set,clr,clk; wire q1,q1_,q2,q2_,q3,q3_; always #50 clk=~clk; initial begin clk<=0; s<=0; r<=0; d<=0; j<=0; k<=0; set<=0; clr<=0; #50 s<=1; r<=0; d<=1; j<=1; k<=0; set<=1; clr<=0; #50 s<=1; r<=0; d<=1; j<=1; k<=0; set<=0; clr<=1; #50 s<=1; r<=0; d<=1; j<=1; k<=0; set<=0;

clr<=0; #50 s<=0; r<=1; d<=0; j<=0; k<=1; set<=0; clr<=0; #50 s<=1; r<=1; d<=0; j<=1; k<=1; set<=0; clr<=0; #400 $stop; end

SRchufa oo(set,clr,clk,r,s,q1,q1_); Dchufa ox(set,clr,clk,d,q2,q2_); JKchufa oy(set,clr,clk,j,k,q3,q3_);

endmodule

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